Staff Engineer - Analog Layout

Micron Technology, Inc; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Micron Technology, Inc in Bengaluru seeks an experienced engineer to lead full-custom layout designs for complex Analog/Mixed-Signal IP blocks. The ideal candidate will have strong expertise in advanced FinFET nodes and a solid background in planar CMOS technologies.

This role involves collaborating with circuit designers, ensuring layout quality, and providing mentorship to junior engineers. A commitment to layout verification and best practices in advanced technology is essential for success.

Qualifications

• Strong experience in advanced FinFET nodes such as TSMC 3nm, 5nm.
• Solid background in planar CMOS technologies for analog robustness.
• Deep understanding of layout-dependent effects and process variability.

Responsibilities

• Lead full-custom layout for complex Analog / Mixed-Signal IP blocks.
• Own layout quality from floor-planning to tape-out.
• Work closely with circuit designers for layout strategies.
• Drive and close DRC, LVS, and reliability checks.
• Provide technical guidance for junior and mid-level engineers.

Skills

FinFET nodes experience

Advanced layout verification

Deep foundry PDK knowledge

CMOS technologies understanding

Job description

Key Responsibilities

• Lead full‑custom layout for complex Analog / Mixed‑Signal IP blocks, including but not limited to:
  • Bandgap references, LDOs and regulators, Charge pumps (positive/negative)
  • PLLs, delay lines, oscillators, IO & PHY‑related analog blocks
  • Temperature sensors, bias circuits
  • ESD protection devices and clamps
• Own layout quality from floor‑planning to tape‑out, ensuring:
  • Device matching and symmetry, noise isolation and substrate strategies
  • Robust power/ground planning
  • Yield, reliability, and DFM compliance
• Work closely with circuit designers to translate performance goals into layout strategies, especially in noise‑sensitive mixed‑signal environments.

Advanced Technology Expertise

• Strong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:
  • Fin quantization awareness
  • Multi‑Vt, multi‑fin strategies
  • Advanced metal stack planning
• Solid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.
• Deep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.

Layout Verification & Signoff

• Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks.
• Review and address issues related to:
  • EM/IR, latch‑up, ESD window compliance
  • Device stress and matching degradation
• Interface with foundry and CAD teams for waiver management and signoff convergence.

Leadership & Mentorship

• Provide technical guidance and design reviews for junior and mid‑level layout engineers.
• Establish and document best‑known methods (BKMs) for AMS layout across nodes.
• Drive IP reuse, layout template development, and methodology improvements.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.