Engineer, IPDev Layout

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad, Telangana, seeks a skilled analog layout designer. In this role, you will be responsible for designing and developing critical layouts and performing verification tasks.

The ideal candidate should have 5 to 8 years of experience in analog/custom layout with expertise in tools like Cadence VLE/VXL and Mentor Graphics. The position emphasizes clear communication and leadership in project settings.

Qualifications

• 5 to 8 years' experience in analog/custom layout build in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Ability to understand build constraints and implement high-quality layouts.

Responsibilities

• Responsible for design and development of critical analog and mixed-signal layouts.
• Perform layout verification like LVS/DRC/Antenna.
• Demonstrate leadership qualities in planning and execution to meet project milestones.

Skills

Analog/custom layout build

Cadence VLE/VXL

Mentor Graphic Calibre DRC/LVS

Understanding of Analog Layout fundamentals

Problem-solving skills in physical verification

Experience in AI-related tools

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence

Mentor Graphics

Job description

Role and Responsibilities

• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for timely delivery of block-level layouts with acceptable quality.
• Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Qualifications

• 5 to 8 years' experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET)
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Hands‑on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier.
• Good understanding of Analog Layout fundamentals (e.g. Matching, Electro‑migration, Latch‑up, coupling, crosstalk, IR‑drop, active and passive static device parasitics, etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area.
• Ability to understand build constraints and implement high‑quality layouts.
• Ability to understand build hierarchy and different architectures for Memory designs.
• Excellent problem‑solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.
• Should be proactive in exploring and leveraging AI‑related tools in day‑to‑day tasks.

Education

BE or MTech in Electronic/VLSI Engineering

Equal Opportunity Employment

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.