Staff Engineer, HIG HBM Layout

Micron Technology; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Micron Technology is looking for a skilled layout designer in Hyderabad, India, with 8 to 15 years of experience in analog/custom layout design. The candidate will be responsible for designing critical analog blocks, performing layout verification, and leading junior team members.

The ideal applicant will have expertise in Cadence VLE/VXL and Mentor Graphics Calibre. A BE or MTech in Electronic/VLSI Engineering is required. This role combines technical excellence with project management skills.

Qualifications

• 8 to 15 years' experience in analog/custom layout design in advanced CMOS process.
• Hands-on experience in creating layouts of critical blocks (e.g., Temperature sensor, PLL, ADC).
• Good understanding of Analog Layout fundamentals like Matching and Electro-migration.

Responsibilities

• Responsible for design and development of critical analog and mixed-signal blocks.
• Perform layout verification like LVS/DRC/Antenna and ensure quality checks.
• Guide junior team members in execution of sub block-level layouts.

Skills

Analog/custom layout design

Cadence VLE/VXL

Mentor Graphic Calibre DRC/LVS

Physical verification

Project management

Education

BE or MTech in Electronic/VLSI Engineering

Job description

Role and Responsibilities

• Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Guide junior team-members in their execution of sub block-level layouts & review their work
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Qualifications / Requirements

• 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET )
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Ability to understand design constraints and implement high-quality layouts.
• Ability to understand design hierarchy and different architectures for Memory designs.
• Excellent command and problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.