Staff Engineer, HIG HBM Layout

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is looking for an experienced Analog Layout Designer. You will design and develop critical analog and mixed-signal layouts, ensuring high-quality and timely deliveries.

The ideal candidate will have 6 to 9 years of experience, expertise in Cadence and Mentor Graphics tools, and strong problem-solving skills. A BE or MTech in Electronic/VLSI Engineering is required. Join us to lead projects and guide junior team members while collaborating with global engineering teams.

Qualifications

• 6 to 9 years' experience in analog/custom layout design in advanced CMOS process.
• Hands-on experience creating layout of critical blocks.
• Good understanding of analog layout fundamentals.
• Excellent verbal and written communication skills.

Responsibilities

• Responsible for design and development of analog and mixed-signal layouts.
• Perform layout verification and quality checks.
• Ensure on-time delivery of layouts with high quality.
• Guide junior team members and contribute to effective project management.

Skills

Analog/custom layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Problem-solving skills

Communication skills

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence

Mentor Graphics

Job description

Role and Responsibilities

• Responsible for design and development of critical analog, mixed-signal, custom digital block, and full-chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for on‑time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Ability to guide junior team‑members in their execution of sub‑block‑level layouts & review critical items.
• Contribute to effective project‑management.
• Effectively communicating with global engineering teams to assure the success of layout project.

Qualifications and Experience

• 6 to 9 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands‑on experience creating layout of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Good understanding of Analog Layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, active and passive static device parasitics, etc.).
• Understanding layout effects on circuit performance (speed, capacitance, power, area).
• Ability to understand design constraints and implement high‑quality layouts.
• Ability to understand design hierarchy and different architectures for memory designs.
• Excellent problem‑solving skills in physical verification of custom layout.
• Multiple tape‑out support experience is advantageous.
• Excellent verbal and written communication skills.
• Education: BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.