Senior Analog Layout Engineer

Cyient; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Cyient in Bengaluru seeks a senior layout engineer specializing in analog and mixed-signal design for 7nm FinFET blocks. You will convert circuit schematics into robust physical layouts, maintain hierarchy, and work closely with design engineers to meet performance and area targets.

The role requires hands-on experience with advanced node challenges, DRC/LVS/PEX, and post-layout verification. You will document methodologies and participate in reviews to drive first-pass silicon success.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical, Microelectronics, or related field.
• Experience with 7nm FinFET layout development and high-speed analog/mixed-signal design.
• Expertise in DRC, LVS, and parasitic extraction (PEX) checks.
• Ability to interpret schematics and design specifications.

Responsibilities

• Create and optimize floorplans for analog and mixed-signal blocks in 7nm FinFET.
• Translate sub-block schematics into physical layouts while preserving hierarchy.
• Perform transistor- and block-level layout for high-speed circuits.
• Ensure layout matches parameterized devices and simulation hierarchy.
• Follow documentation, feedback, and back-annotation during layout.
• Resolve DRC violations until layout is clean.
• Resolve LVS discrepancies until sign-off.
• Ensure compliance with foundry design rules and reliability.
• Generate extracted netlists for post-layout simulations.
• Collaborate with Design Engineers to support verification.
• Document layout methodologies and implementation notes.
• Participate in design reviews and implement corrective actions.
• Optimize layout for area, matching, parasitics, SI and manufacturability.

Skills

7nm FinFET layout

Analog & mixed-signal layout

DRC/LVS/PEX/ERC

Post-layout netlists

Analog layout techniques

Device matching

Parasitic optimization

Multi-patterning awareness

Pattern matching

Education

Bachelor's in Electronics/Electrical/Microelectronics

Master's in Electronics/Electrical/Microelectronics

Electrical Engineering background

Tools

Cadence Virtuoso Layout Suite

Calibre DRC/LVS/PEX

Synopsys IC Validator

Custom Compiler

Cadence Pegasus

ADE

Job description

Key Responsibilities

• Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology.
• Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.
• Perform detailed transistor-level and block-level layout implementation for high-speed circuits.
• Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis.
• Follow design documentation, review comments, customer feedback, and back-annotation requirements during layout execution.
• Perform and resolve Design Rule Check (DRC) violations until the layout is fully clean.
• Perform and resolve Layout Versus Schematic (LVS) discrepancies until successful signoff.
• Ensure layouts comply with all foundry-specific design rules and reliability requirements.
• Generate extracted netlists for post-layout simulations and back-annotation activities.
• Work closely with Design Engineers (DEs) to support post-layout verification and performance closure.
• Document layout methodologies, notes, and implementation details in block review documents.
• Participate in design reviews and implement corrective actions resulting from layout reviews.
• Optimize layout for area, matching, parasitics, signal integrity, electromigration (EM), and manufacturability.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• Strong experience in 7nm FinFET technology node layout development.
• Proven expertise in high-speed analog and mixed-signal layout design.
• Hands-on experience with advanced node layout challenges including:
  • Multi-patterning awareness
  • Device matching
  • Parasitic optimization
  • Reliability rules
• Strong understanding of:
  • DRC
  • LVS
  • Parasitic extraction (PEX)
  • ERC checks
• Experience generating extracted netlists and supporting post-layout simulations.
• Excellent understanding of analog layout techniques:
  • Common centroid
  • Interdigitation
  • Symmetry
  • Matching
  • Shielding
  • Guard rings
• Ability to read and interpret circuit schematics and design specifications.

Preferred Skills

• Experience with advanced nodes such as 3nm, 4nm, 5nm, 6nm, 7nm, 10nm, or 12nm FinFET.
• Experience in layouts for:
  • PLLs
  • High-speed SerDes
  • Clocking circuits
  • Data converters (ADC/DAC)
  • High Bandwidth Memory
  • RF or mixed-signal IPs
• Knowledge of EMIR analysis and reliability verification.
• Familiarity with process variation and layout-dependent effects (LDE).
• Experience working with global semiconductor customers.

EDA Tools Expertise

• Cadence Virtuoso Layout Suite
• Calibre DRC/LVS/PEX
• Synopsys IC Validator
• Custom Compiler
• Cadence Pegasus
• Analog Design Environment (ADE)

Key Competencies

• Strong attention to detail
• Layout quality ownership
• Problem-solving and debugging skills
• Effective communication with cross-functional teams
• Ability to handle multiple design blocks simultaneously
• Commitment to first-pass silicon success

Nice to Have

• Experience with 5nm/3nm technology nodes.
• Knowledge of automation or scripting (SKILL, Perl, Python, Tcl).
• Experience in IP development for high-performance computing, networking, or AI applications.

Keywords: Analog Layout, Mixed-Signal Layout, FinFET, 7nm, High-Speed Layout, DRC, LVS, PEX, Floorplanning, Cadence Virtuoso, Calibre, SerDes, PLL, HBM.