Senior Engineer- DEG Layout

1840 Micron Tech. OP India LLP; Bengaluru; On-site; INR 111,600 - 167,400; Full time

Job summary

1840 Micron Tech. OP India LLP in Bengaluru is seeking a skilled layout designer with 5 to 8 years of experience in analog and mixed-signal designs. The role includes responsibilities for layout design and verification, leading projects, and optimizing layout processes using AI tools.

The ideal candidate will have expertise in Cadence VLE/VXL and Mentor Graphics Calibre, with a solid understanding of analog layout fundamentals. Competitive communication skills are essential for effective collaboration with global teams.

Join us to contribute to innovative layout projects with a focus on quality and efficiency.

Qualifications

• 5 to 8 years of experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS is essential.
• Hands-on experience with temperature sensors, PLL, ADC, DAC, and more.

Responsibilities

• Responsible for layout design and development of critical analog mixed-signal blocks.
• Perform layout verification including LVS, DRC, and quality checks.
• Demonstrate leadership in planning and execution to meet project schedules.

Skills

Analog/custom layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Layout fundamentals understanding

Problem-solving skills

Communication skills

Job description

Our vision is to transform how the world uses information to enrich life for all.

Role and Responsibilities

• Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level.
• Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation.
• Responsible for development of digital block layouts using auto placement and route tools.
• Responsible for basic understanding of skill coding and automation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.
• Support developing team members in their handling of Sub block-level layouts and review their work.
• Contribute to effective project-management.
• Effectively communicate with Global engineering teams to assure the success of layout project.
• Responsible for reducing the layout effort by using AI tools.

Qualifications

• 5 to 8 year experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS is a must.
• Hands on experience creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
• Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.).
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand design constraints and implement high-quality layouts.
• Excellent command and problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience is an added advantage.
• Excellent verbal and written communication skills.
• Automate layout execution tasks using AI.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.