Staff Engineer- HIG HBM Layout

Micron Technology, Inc; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Micron Technology, Inc is seeking a Staff Engineer in Hyderabad to design and develop critical analog and mixed-signal layouts. The ideal candidate will have 8 to 15 years of experience in advanced CMOS processes and expertise in Cadence and Mentor Graphic tools.

Your primary responsibilities include layout verification, guiding junior members, and ensuring on-time delivery of high-quality designs. A BE or MTech in Electronic/VLSI Engineering is required. Join our dynamic team to contribute effectively to innovative projects.

Qualifications

• 8 to 15 years' experience in analog/custom layout design in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Good understanding of analog layout fundamentals.

Responsibilities

• Responsible for design and development of critical analog, mixed-signal layouts.
• Perform layout verification like LVS/DRC/Antenna, quality check.
• Guide junior team members in execution and review of layouts.

Skills

Analog layout design

Mixed-signal design

Leadership

Problem-solving

Communication

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Graphic Calibre DRC/LVS

Job description

Req. ID: JR99594 Staff Engineer, HIG HBM Layout

Role and Responsibilities

• Responsible for design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in a multiple project environment.
• Guide junior team-members in their execution of sub block-level layouts & review their work.
• Contribute to effective project-management.
• Effectively communicate with global engineering teams to assure the success of layout project.

Qualifications / Requirements

• 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Hands‑on experience in creating layouts of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, ref generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Good understanding of analog layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices, etc.).
• Understanding layout effects on the circuit such as speed, capacitance, power, and area.
• Ability to understand design constraints and implement high‑quality layouts.
• Ability to understand design hierarchy and different architectures for memory designs.
• Excellent command and problem‑solving skills in physical verification of custom layout.
• Multiple tape‑out support experience will be an added advantage.
• Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.