Staff Engineer, HIG HBM Layout

3M HEALTHCARE; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

3M HEALTHCARE is seeking a senior IC Layout Engineer to design analog, mixed‑signal and custom digital blocks, ensuring full chip level integration. You will lead layout planning, estimation, and execution in a multi‑project environment, guiding juniors and coordinating with global teams.

The role requires 8–15 years in analog layout across advanced CMOS nodes, with hands‑on Cadence VLE/VXL and Calibre DRC/LVS proficiency. Strong verification and communication skills are essential.

Qualifications

• 8 to 15 years of experience in analog/custom layout design in advanced CMOS process across various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS.
• Hands‑on experience creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, etc.
• Good understanding of analog layout fundamentals (matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop).
• Excellent command and problem‑solving skills in physical verification of custom layout.

Responsibilities

• Design and develop analog, mixed‑signal, custom digital blocks and full chip level integration support.
• Ensure on‑time delivery of block‑level layouts with acceptable quality.
• Lead planning, area/time estimation, scheduling and delegation in multi‑project environment.
• Guide junior team members in sub‑block layouts and reviews.
• Communicate effectively with global engineering teams to assure layout project success.

Skills

Analog layout

CMOS layout

Layout verification

Memory design architectures

Project management

Mentoring / guiding juniors

Communication

Design hierarchy

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Job description

Role and Responsibilities

• Responsible for design and development of critical analog, mixed‑signal, custom digital blocks and full chip level integration support.
• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design.
• Perform layout verification such as LVS/DRC/antenna, quality checks and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in a multi‑project environment.
• Guide junior team members in execution of sub‑block‑level layouts and review their work.
• Contribute to effective project management.
• Effectively communicate with global engineering teams to assure the success of layout projects.

Qualifications

• 8 to 15 years of experience in analog/custom layout design in advanced CMOS process across various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands‑on experience creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Good understanding of analog layout fundamentals (matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices).
• Understanding of layout effects on circuit performance such as speed, capacitance, power and area.
• Ability to understand design constraints and implement high‑quality layouts.
• Ability to understand design hierarchy and different architectures for memory designs.
• Excellent command and problem‑solving skills in physical verification of custom layout.
• Experience with multiple tape‑out support is an added advantage.
• Experience managing multiple layout projects, ensuring quality checks at all stages of layout development.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or disability status.