Senior Layout Engineer - DPG Layout

Micron Technology; Hyderabad; On-site; INR 600,000 - 1,000,000; Full time

Job summary

Micron Technology in Hyderabad is hiring a skilled analog layout designer with 3+ years of experience in CMOS processes. The role involves implementing and verifying layouts for analog and mixed-signal circuits, utilizing Cadence Virtuoso tools. Successful candidates will have a solid understanding of layout fundamentals and be adept at using AI methodologies to improve layout efficiency.

This position requires strong problem-solving skills and the ability to interpret design constraints effectively. A B.Tech or M.Tech in relevant fields is essential.

Qualifications

• 3+ years of experience in analog/custom layout design in advanced CMOS processes.
• Hands-on experience with Cadence Virtuoso and Calibre DRC/LVS.
• Strong understanding of analog layout fundamentals, including matching and symmetry techniques.

Responsibilities

• Implement design and physical implementation of analog and mixed-signal blocks.
• Deliver high-quality block-level layouts under guidance from senior engineers.
• Use AI tools to generate or refine SKILL/Python/TCL scripts.

Skills

Analog layout design

Cadence Virtuoso

Layout verification

AI-driven automation

Problem-solving

Education

B.Tech in Electronics

M.Tech in VLSI Design

Tools

Calibre DRC/LVS

Job description

Responsibilities

• Implement the design and physical implementation of analog, mixed-signal, custom digital blocks and support full-chip integration, using a combination of traditional layout expertise.
• Own block-level layout execution with strong focus on quality, turnaround time and design intent.
• Perform layout verification activities, including DRC, LVS, Antenna checks, Yield and quality checks.
• Deliver on‑time, high‑quality block‑level layouts under the guidance from senior engineers.
• Use prompt‑based AI tools to generate or refine SKILL/Python/TCL scripts, automate repetitive layout and verification tasks to reduce manual effort and improve layout consistency.
• Support custom and digital layout integration, using semi‑custom tools to accelerate ECOs, alignment, and integration‑level updates.
• Collaborate closely with Design, Verification, CAD, and senior layout engineers, clearly communicating layout status and risks.
• Assist in reviewing sub-block layouts from engineers developing their skills and share helpful techniques within the team.

Job Requirements

• 3+ year experience in analog/custom layout design in advanced CMOS process.
• Hands‑on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.
• Experience in layout of critical analog and mixed‑signal blocks like Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps.
• Exposure to memory layout environments, including DRAM, SRAM, CAM or OTP is desirable.
• Solid understanding of analog layout fundamentals, including matching and symmetry techniques, electromigration, latch‑up, IR‑drop, coupling, crosstalk and parasitic effects.
• Understanding of layout impact on circuit performance, including speed, capacitance, power, and area.
• Ability to interpret design constraints and translate them into robust, manufacturable layouts.
• Hands‑on experience in developing or applying AI‑driven automation and AI‑assisted methodologies to improve efficiency and quality of physical layout tasks.
• Strong problem‑solving skills in physical layout verification and debug.

Education

• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering.
• M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.