Analog Layout Engineer

Digicomm Semiconductor INC; India; On-site; INR 250,000 - 450,000; Full time

Job summary

Digicomm Semiconductor INC in India seeks an experienced analog/mixed-signal layout designer for advanced FinFET processes. The role emphasizes ownership of PNR flow, routing, and timing closure across complex blocks, including SERDES, PHY, HDMI, PLL, ADC, and DAC.

Candidates should excel in CMOS/Bi-CMOS/SOI/FinFET processes and AMS IP integration. The ideal professional will lead a small team, drive layout quality, mentor peers, and collaboratively resolve congestion and verification challenges

Qualifications

• Extensive experience in analog/mixed-signal layout in FinFET nodes.
• Proficient in PNR flow, CTS, routing and timing closure.
• Hands-on in blocks like SERDES, PHY, HDMI, PLL, ADC/DAC, LDO, Bandgap, references.
• Deep knowledge of CMOS/Bi-CMOS/SOI/FinFET processes.
• Experience in AMS IP integration for full-chip layouts per guidelines.
• Strong problem-solving in routing congestion and physical verification.

Responsibilities

• Lead layout execution with timely and high-quality outputs.
• Mentor and guide layout team members and review work for quality and delivery.

Skills

Analog Layout

Mixed-Signal Design

FinFET Processes

PNR Flow

Routing & Timing Closure

Leadership & Mentoring

Tools

Cadence

Mentor Graphics

VirtuosoXL

Job description

• Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm
• Expertise on complete PNR flow CTS,routing, Timing Closure.
• Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
• Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
• Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process
• Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
• Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout
• Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.
• Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layoutssuch as speed, capacitance, power, noise, and area
• Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL
• Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery
• Responsible for timely and quality execution of Custom Layout design
• Excellent communication skills and proactive at work