Analog Layout Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru, India seeks an experienced Analog Layout Engineer to design high-performance full-custom layouts for advanced nodes. You will own layout execution from device level to tapeout, focusing on matching, reliability and manufacturability to achieve first-pass silicon success.

The role requires 5–10 years in analog full custom layout, expertise in device matching, common centroid techniques, shielding, and advanced routing, using Cadence Virtuoso XL/Studio

Qualifications

• 5–10 years of hands-on experience in analog full custom layout.
• Strong expertise in device matching, common centroid, interdigitation, shielding, guard rings.
• Experience with analog IPs such as PLL, LDO, Bandgap, ADC/DAC, SerDes, DDR PHY, PMIC, USB, PCIe.
• Proficiency with Cadence Virtuoso XL/Studio, Calibre/PVS/ICV, and extraction tools Quantus or StarRC.
• Understanding of DRC/LVS/ERC, DFM, Antenna, EM/IR, PERC.
• Experience with FinFET technologies (16nm/7nm/5nm/3nm) and layout signoff.
• Scripting with SKILL, Tcl, or Python is a plus.

Responsibilities

• Develop full-custom analog layouts for high-performance IPs (PLL, LDO, Bandgap, ADC, DAC, SerDes, DDR PHY, PMIC, IOs).
• Perform device placement, routing, floorplanning, shielding, and guard rings.
• Drive layout closure for DRC, LVS, ERC, Antenna, DFM, Density, EM/IR, PERC.
• Optimize layouts for matching, noise isolation, IR drop, electromigration, yield, and performance.
• Collaborate with Circuit Design, Reliability, Physical Verification, and Process teams to hit PPA targets.
• Support layout migration across tech nodes and contribute to layout methodology and automation.

Skills

Analog Full Custom Layout

Device matching

Common centroid

Interdigitation

Shielding

Guard rings

Deep N-Well

Substrate isolation

Analog routing techniques

Scripting (SKILL/Tcl/Python)

Tools

Cadence Virtuoso XL/Studio

Calibre/PVS/ICV

Quantus

StarRC

Job description

Design and implement high-performance Analog/Mixed-Signal layouts for advanced-node SoCs. Own layout execution from device level to tapeout while delivering optimal matching, reliability, manufacturability, and first-pass silicon success.

What You’ll Do

• Develop full-custom Analog Layouts for high-performance IPs including PLL, LDO, Bandgap, ADC, DAC, SerDes, DDR PHY, PMIC, Data Converters, IOs, and Clocking Circuits.
• Perform device placement, routing, floorplanning, shielding, guard ring implementation, common-centroid matching, interdigitation, and parasitic-aware optimization.
• Drive layout closure for DRC, LVS, ERC, Antenna, DFM, Density, EM/IR, PERC, and Reliability.
• Optimize layouts for matching, noise isolation, IR drop, electromigration, yield, and performance.
• Collaborate with Circuit Design, Reliability, Physical Verification, and Process teams to achieve PPA and silicon targets.
• Support layout migration across technology nodes and contribute to layout methodology, automation, and best practices.

What You Bring

• 5–10 years of hands‑on experience in Analog Full Custom Layout.
• Strong expertise in device matching, common centroid, interdigitation, shielding, guard rings, deep N‑Well, substrate isolation, and analog routing techniques.
• Experience with Analog IPs such as PLL, LDO, Bandgap, ADC/DAC, SerDes, DDR PHY, PMIC, USB, PCIe, MIPI, or High-Speed IOs.
• Hands‑on experience with Cadence Virtuoso XL/Studio, Calibre/PVS/ICV, and extraction tools such as Quantus or StarRC.
• Strong understanding of DRC/LVS/ERC, DFM, Antenna, EM/IR, PERC, and advanced-node layout challenges.
• Experience with FinFET technologies (16nm/7nm/5nm/3nm) and physical signoff methodologies.
• Scripting experience using SKILL, Tcl, or Python is an added advantage.

Preferred

• Experience in Memory Layout, High-Speed Interface Layout, or 3DIC/TSV.
• Exposure to ESD, Reliability, Low-Power Design, and layout automation.