STAFF ENG-HIG-HBM-LAYOUT

Micron Technology, Inc; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Micron Technology, Inc is seeking a highly motivated individual for IC layout design in Hyderabad, India. The role requires leading the design and development of complex analog, mixed-signal, and digital blocks, ensuring timely delivery and high quality of layouts.

Candidates should have 8–15 years of experience in layout design and expertise in Cadence and Mentor Graphics tools. A BE or MTech in Electronic/VLSI Engineering is required. This position offers opportunities for mentorship and collaboration with global engineering teams.

Qualifications

• 8–15 years of experience in Memory/Analog/Custom layout design.
• Strong expertise in layout verification tools for DRC/LVS.
• Experience in designing critical Memory/Analog and mixed-signal blocks.

Responsibilities

• Lead design and development of complex analog and digital blocks.
• Manage multiple priorities and deliver results under tight timelines.
• Provide mentorship and guidance to junior team members.

Skills

IC layout design

Cadence VLE/VXL

Mentor Graphics Calibre

Memory layout principles

Problem-solving skills

Education

BE or MTech in Electronic/VLSI Engineering

Job description

Role and Responsibilities

• Highly motivated, detail‑oriented and systematic approach to IC layout design.
• Perform layout verification (LVS, DRC, antenna checks) with thorough quality reviews and documentation.
• Lead the design and development of complex analog, mixed‑signal, and digital blocks, as well as full‑chip level integration.
• Ensure timely delivery of high‑quality, block‑level layouts that meet project milestones and design specifications.
• Collaborate with global engineering teams to execute and integrate layout projects successfully.
• Provide technical guidance and mentorship to junior team members, reviewing sub‑block layouts and supporting their development.
• Manage multiple priorities and deliver results under tight timelines while demonstrating leadership in planning, scheduling and execution.
• Contribute actively to project management and cross‑functional coordination.

Qualification / Requirements

• 8–15 years of experience in Memory / Analog / Custom layout design across advanced CMOS process nodes, including Planar and FinFET technologies.
• Strong expertise in Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS verification.
• Hands‑on experience designing critical Memory / Analog and mixed‑signal blocks such as array layout, decoder, control logic, IOs, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps, current mirrors, comparators, and differential amplifiers.
• Solid understanding of memory/analog layout principles, including bit cell, addressing, banking, matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.
• Ability to assess and mitigate layout impacts on circuit performance—speed, capacitance, power, and area.
• Familiarity with design hierarchies and memory layout architectures is a plus.
• Strong problem‑solving skills in physical verification and debugging of custom layouts.
• Prior involvement in multiple successful tapeouts is highly desirable.
• Proven ability to manage multiple layout projects, ensuring quality and timely delivery at all stages.
• Excellent verbal and written communication skills, with the ability to collaborate effectively across global teams.

Education

• BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.