STAFF ENG-HBM-LAYOUT

Micron Technology, Inc; Hyderabad; On-site; INR 2,000,000 - 3,200,000; Full time

Job summary

Micron Technology, Inc in Hyderabad is seeking a Semiconductor Design Engineer with 8–15 years of CMOS analog/custom layout experience. You will design and optimize layout blocks, participate in tape-out, and coordinate with global teams to ensure on-time delivery and quality.

Required are Cadence VLE/VXL and Mentor Calibre DRC/LVS expertise, a BE/MTech in Electronics/VLSI, and the ability to drive sub-block layouts and reviews across multiple projects.

Qualifications

• 8–15 years of analog/custom layout design in advanced CMOS processes across planar/FinFET nodes.
• Experience in reticle development and full-chip verification.
• Strong understanding of layout fundamentals and how they affect circuit performance.

Responsibilities

• Design and develop critical analog/custom layout blocks and co-optimization objectives.
• Lead tape-out of PWF reticle designs and full-chip integration support.
• Engage with cross-functional teams to capture advanced packaging requirements.

Skills

Analog/Custom Layout

Leadership

Layout verification

AI for project execution

Problem solving

Communication

Tape-out experience

Education

BE / MTech in Electronics / VLSI

Tools

Cadence VLE

Cadence VXL

Mentor Calibre DRC/LVS

Job description

Role and Responsibilities

• Responsible for design and development of critical design and co‑optimization objectives, mixed‑signal, custom digital block and full chip level integration support.
• Build and tapeout PWF reticle design.
• Engage with scribe design team to capture advanced packaging requirements and review.
• TSV design engagement with HIG‑HBM DTPCO teams (electrical, thermal and mechanical performance).
• Create and maintain DFMEA related to advanced packaging process steps like PWF and die stacking.
• Be highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design.
• Perform layout verification such as LVS/DRC/antenna, quality check and documentation.
• Ensure on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation and execution to meet project schedule and milestones in a multiple‑project environment.
• Guide junior team members in executing sub‑block‑level layouts and review their work.
• Contribute to effective project management.
• Effectively communicate with global engineering teams to assure the success of layout projects.

Qualifications and Requirements

• 8 to 15 years’ experience in analog/custom layout design in advanced CMOS process, across various technology nodes (planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphical Calibre DRC/LVS.
• Hands‑on experience creating layout of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Experience in reticle development and full chip verification.
• Capability to automate or use AI features for fast and efficient project execution.
• Good understanding of layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices).
• Understanding of layout effects on circuit performance such as speed, capacitance, power and area.
• Excellent command and problem‑solving skills in physical verification of custom layout.
• Multiple tape‑out support experience is an added advantage.
• Experience managing multiple layout projects, ensuring quality checks at all stages of layout development.
• Excellent verbal and written communication skills.

Education

• BE or MTech in Electronic/VLSI Engineering.

Job Profile(s): Semiconductor Design Engineer 4

Relocation level: (TBD)

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.