Engineer, HIG HBM Layout

Micron Technology; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Micron Technology in Hyderabad is seeking an experienced IC Layout Engineer to design and develop critical analog and mixed-signal layouts. The role involves layout verification, guiding junior team members, and ensuring on-time delivery of high-quality layouts.

Candidates should have 3 to 7 years of experience with advanced CMOS processes and expertise in Cadence and Mentor Graphics tools. A BE or MTech in Electronic/VLSI Engineering is required, along with excellent problem-solving skills and effective communication in a global team environment.

Qualifications

• 3 to 7 years' experience in memory/custom layout design in advanced CMOS process.
• Hands-on experience creating layouts of critical blocks like PLL, ADC, DAC, etc.
• Excellent problem-solving skills in physical verification of custom layout.

Responsibilities

• Design and develop critical analog and mixed-signal layouts.
• Perform layout verification including LVS/DRC.
• Guide junior team members in layout execution.

Skills

Memory/custom layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Analog layout fundamentals

Problem-solving

Verbal and written communication skills

Education

BE or MTech in Electronic/VLSI Engineering

Job description

Role and Responsibilities

• Responsible for design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in a multiple project environment.
• Guide junior team‑members in their execution of sub‑block‑level layouts & review their work.
• Contribute to effective project-management.
• Effectively communicate with global engineering teams to assure the success of layout project.

Qualification/Requirements

• 3 to 7 years' experience in memory/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS is a must.
• Hands‑on experience in creating layout of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, ref generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Good understanding of analog layout fundamentals (cf. matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, active and passive static device parasitics, etc.).
• Understanding layout effects on the circuit such as speed, capacitance, power and area.
• Ability to understand design constraints and implement high‑quality layouts.
• Ability to understand design hierarchy and different architectures for memory designs.
• Excellent problem‑solving skills in physical verification of custom layout.
• Multiple tape‑out support experience will be an added advantage.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].