Engineer, IPDev Layout

Micron Technology; Hyderabad; On-site; INR 2,000,000 - 3,600,000; Full time

Job summary

Micron Technology in Hyderabad seeks an experienced analog/layout engineer to design and develop analog, mixed-signal, and custom digital blocks for full-chip integration. The role requires hands-on Cadence VLE/VXL and Calibre DRC/LVS expertise, strong analog fundamentals, and leadership in delivering high-quality layouts.

Excellent communication and proactive use of AI tools in day-to-day tasks are valued, with an emphasis on timely block-level delivery across a multi-project environment.

Qualifications

• 5 to 8 years' experience in analog/custom layout in advanced CMOS process.
• Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS is a must.
• Hands-on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier.
• Good understanding of Analog Layout fundamentals (Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitics).
• Understanding layout effects on speed, capacitance, power and area.
• Ability to understand build hierarchy and architectures for Memory designs.
• Excellent problem-solving in physical verification of custom layout.
• Tape-out experience is a plus.
• Excellent verbal and written communication skills.
• Proactive in exploring AI-related tools in day-to-day tasks.

Responsibilities

• Design and development of analog, mixed-signal, custom digital blocks and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for timely delivery of block-level layouts with acceptable quality.
• Demonstrate leadership in planning, estimation, scheduling, and execution across multiple projects.
• Contribute to effective project-management.
• Communicate effectively with global engineering teams to assure layout project success.

Skills

Analog Layout

Mixed-Signal Design

Block-level Layout

Leadership

Communication

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Role and Responsibilities

• Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
• Responsible for timely delivery of block-level layouts with acceptable quality.
• Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Contribute to effective project-management.
• Effectively communicating with Global engineering teams to assure the success of layout project.

Qualification/Requirements

• 5 to 8 years' experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET)
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
• Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand build constraints and implement high-quality layouts
• Ability to understand build hierarchy and different architectures for Memory designs.
• Excellent problem-solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Excellent verbal and written communication skills.
• Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks.

Education

BE or MTech in Electronic/VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.