SENIOR ENG-HIG-HBM-LAYOUT

Micron Technology, Inc; Hyderabad; On-site; INR 3,000,000 - 4,200,000; Full time

Job summary

Micron Technology, Inc is seeking a Semiconductor Design Engineer 3 with 6+ years of analog/custom layout experience in advanced CMOS processes. You will craft critical blocks, ensure tight LVS/DRC checks, and drive layouts through tape-out with leadership across multiple projects.

Strong collaboration with global teams is required to meet tight schedules. The role demands deep expertise in Cadence and Mentor tools, along with a hands‑on approach to block‑level layout and verification, guiding

Qualifications

• 6+ years' experience in analog/custom layout development in CMOS processes across planar/FinFET nodes.
• Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS.
• Hands‑on experience in crafting layouts of critical blocks (temp sensors, PLL, ADC/DAC, LDO, Bandgap, references, current mirrors).
• Strong understanding of analog layout fundamentals (matching, EM, latch‑up, crosstalk, IR‑drop, parasitics).
• Ability to understand build constraints and develop high‑quality layouts.

Responsibilities

• Build and tapeout analog, mixed‑signal, and custom digital blocks with full chip level integration support.
• Tapeout PWF Reticles and verify layouts.
• Collaborate on Advanced Packaging requirements; engage in TSV build with cross‑functional teams.
• Lead layout planning, area/time estimation, scheduling, and execution across multi‑project environments.
• Guide junior layout engineers and review sub‑block layouts for quality and consistency.
• Communicate with global teams to ensure layout project success.

Skills

Analog layout

Custom layout

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Layout verification

Team leadership

Project planning

Cross-team collaboration

Communication skills

EM considerations

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Role and Responsibilities

• Build and develop critical analog, mixed-signal, custom digital blocks, and provide full chip level integration support.
• Build and tapeout PWF Reticles.
• Collaborate with the Scribe Build team to implement and review Advanced Packaging requirements.
• Engage in TSV build with HIG-HBM DTPCO teams, ensuring flawless electrical, thermal, and mechanical performance.
• Exhibit a highly motivated, diligent, meticulous, and methodical approach in IC layout development.
• Perform layout verification like LVS/DRC/Antenna checks, quality control, and documentation.
• Ensure timely delivery of block-level layouts with outstanding quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and achievements in a multi-project environment.
• Guide less experienced team members in their completion of sub-block-level layouts and review their work.
• Contribute to effective project management.
• Communicate effectively with global engineering teams to ensure the success of layout projects.

Qualifications and Requirements

• 6+ years' experience in analog/custom layout development in advanced CMOS processes across various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS.
• Hands‑on experience in crafting layouts of critical blocks such as Temperature sensors, PLL, ADC, DAC, LDO, Bandgap, Reference Generators, Charge Pumps, Current Mirrors, Comparators, Differential Amplifiers, etc.
• Strong understanding of analog layout fundamentals (e.g., matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices).
• Ability to understand and implement build constraints to develop high‑quality layouts.
• Knowledge of build hierarchy and various memory build architectures.
• Excellent problem‑solving skills in physical verification of custom layouts.
• Multiple tape‑out support experience is advantageous.
• Capability in managing multiple layout projects with strict quality checks at all development stages.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering

Job Profile(s)

Semiconductor Design Engineer 3

Relocation

Relocation level: (TBD)

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran, or disability status. Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.