STAFF ENG-HBM-LAYOUT

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad invites an experienced Layout Design Engineer to drive analog/custom layout across CMOS nodes, with emphasis on PWF reticle design and full-chip integration.

The role requires 8–15 years of hands-on experience, expertise in Cadence and Calibre tools, and mentoring of junior designers. You will collaborate with global teams on complex packaging and verification tasks.

Qualifications

• 8–15 years in analog/custom layout design across CMOS nodes.
• Experience with planar and FinFET processes.
• Proficient in LVS/DRC and tape-out workflows.
• Ability to guide sub-block layout execution.

Responsibilities

• Design and develop blocks, co-optimization for mixed-signal and full-chip integration.
• Build and tape-out PWF reticle designs.
• Collaborate with Scribe Design to capture packaging requirements.
• Review TSV design with HIG-HBM DTPCO teams.
• Create and maintain DFMEA for packaging steps like PWF and die stacking.
• Perform layout verification and quality documentation.
• Plan and manage milestones in a multi-project environment.
• Guide junior team members in sub-block layout execution.
• Contribute to project management and cross-team communication.

Skills

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Analog Layout

Full-chip verification

Tape-out design

Team mentoring

Education

BE/MTech in Electronic/VLSI Eng

Tools

Cadence tools

Mentor Graphics Calibre

Job description

Layout Design Engineer – Hyderabad, India

Join Micron Technology’s HBM Team to design and develop critical analog, custom digital, and full‑chip integration solutions for high‑bandwidth memory and AI/HP computing applications.

Role & Responsibilities

• Design and develop critical blocks, co‑optimization objectives for mixed‑signal, custom digital, and full‑chip integration support.
• Build and tape‑out PWF reticle designs.
• Collaborate with the Scribe Design team to capture advanced packaging requirements.
• Review TSV design engagement with HIG‑HBM DTPCO teams (electrical, thermal, mechanical performance).
• Create and maintain DFMEA for advanced packaging process steps like PWF, die stacking, etc.
• Perform layout verification (LVS/DRC/antenna) and quality documentation.
• Ensure on‑time delivery of block‑level layouts with acceptable quality.
• Plan, estimate areas/time, schedule, delegate, and execute to meet project milestones in a multi‑project environment.
• Guide junior team members in sub‑block layout execution and review.
• Contribute to effective project management and effective communication with global engineering teams.

Qualifications & Requirements

• 8–15 years of experience in analog/custom layout design in advanced CMOS process (Planar, FinFET) across various technology nodes.
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands‑on experience creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Hands‑on experience in reticle development and full‑chip verification.
• Capability to automate or use AI features for fast and efficient project execution.
• Strong understanding of layout fundamentals (matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, passive parasitic devices).
• Understanding of layout effects on circuit performance (speed, capacitance, power, area).
• Excellent problem‑solving skills in physical verification of custom layout.
• Multiple tape‑out support experience is an added advantage.
• Experience managing multiple layout projects and ensuring quality checks at all stages.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.