Senior /Staff AMS Layout engineer-DPG-LPDDR

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad seeks an experienced layout engineer to own analog and mixed‑signal LPDDR PHY blocks across PVT conditions. You will lead high‑speed layout for data lanes, manage SI challenges, and collaborate with circuit teams to ensure first‑pass silicon success.

Seeking 10+ years in analog and high‑speed layout with strong experience in scalable, symmetric array architectures and layout‑aware design decisions. On‑site role in Hyderabad, India.

Responsibilities

• Own and drive custom analog and mixed‑signal layout for critical LPDDR PHY blocks, including datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy.
• Implement and deliver critical analog blocks and LPDDR/high‑speed interfaces at advanced technology nodes with 10+ years of hands‑on experience in custom analog and high‑speed layout design.
• Lead high‑speed LPDDR interface layout execution, solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
• Architect and implement scalable array‑based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi‑channel scalability.
• Drive integration of custom digital and mixed‑signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), optimizing clocking, congestion management, and isolation from sensitive analog regions.
• Lead layout‑aware co‑design with circuit teams, enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective.
• Establish robust power distribution, grounding, and isolation strategies, including guard rings, deep N‑well usage, decoupling, and domain separation for high‑speed and analog‑sensitive regions.
• Own physical verification and signoff closure: DRC/LVS, parasitic extraction, and simulation correlation to ensure silicon‑accurate performance.
• Drive post‑layout optimization and ECOs, resolving margin, yield, and manufacturability challenges while ensuring JEDEC compliance.
• Collaborate cross‑functionally with architecture, circuit, verification, and silicon debug teams to enable first‑pass silicon success and high‑volume manufacturability.
• Own and drive PPA optimization, delivering measurable improvements in power efficiency, area utilization, and performance.
• Mentor engineers and contribute to layout methodologies and best practices, including VXL‑compatible flows, design reviews, and continuous improvement initiatives.
• Leverage automation and advanced techniques: apply scripting (SKILL/Python/TCL) to improve productivity and use AI/ML concepts as a value‑add for data‑driven optimization and layout automation.

Job description

Job Responsibilities

• Own and drive custom analog and mixed‑signal layout for critical LPDDR PHY blocks, including datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy.
• Implement and deliver critical analog blocks and LPDDR/high‑speed interfaces at advanced technology nodes with 10+ years of hands‑on experience in custom analog and high‑speed layout design.
• Lead high‑speed LPDDR interface layout execution, solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
• Architect and implement scalable array‑based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi‑channel scalability.
• Drive integration of custom digital and mixed‑signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), optimizing clocking, congestion management, and isolation from sensitive analog regions.
• Lead layout‑aware co‑design with circuit teams, enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective.
• Establish robust power distribution, grounding, and isolation strategies, including guard rings, deep N‑well usage, decoupling, and domain separation for high‑speed and analog‑sensitive regions.
• Own physical verification and signoff closure: DRC/LVS, parasitic extraction, and simulation correlation to ensure silicon‑accurate performance.
• Drive post‑layout optimization and ECOs, resolving margin, yield, and manufacturability challenges while ensuring JEDEC compliance.
• Collaborate cross‑functionally with architecture, circuit, verification, and silicon debug teams to enable first‑pass silicon success and high‑volume manufacturability.
• Own and drive PPA optimization, delivering measurable improvements in power efficiency, area utilization, and performance.
• Mentor engineers and contribute to layout methodologies and best practices, including VXL‑compatible flows, design reviews, and continuous improvement initiatives.
• Leverage automation and advanced techniques: apply scripting (SKILL/Python/TCL) to improve productivity and use AI/ML concepts as a value‑add for data‑driven optimization and layout automation.

Equal Opportunity Employment

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.