Sr AMS Layout Engineer-DPG-LPDDR

Micron Technology, Inc; Hyderabad; On-site; INR 1,200,000 - 1,600,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Paid time-off

Paid holidays

Job summary

Micron Technology, Inc in Hyderabad is looking for a Senior AMS Layout Engineer to own the design and layout of critical analog blocks for LPDDR PHYs. The ideal candidate will possess over 6 years of hands-on experience in analog and mixed signal design, along with strong collaboration skills.

Micron offers a comprehensive range of benefits, including medical, dental, and paid time-off, supporting the well-being and professional growth of team members.

Qualifications

• 6+ years of solid hands-on experience in analog and mixed signal, high-speed serial links.
• Strong understanding of layout best practices and DRC/LVS closure.

Responsibilities

• Own the custom analog and mixed signal layout for LPDDR PHYs.
• Execute high-speed LPDDR interface layout addressing signal integrity challenges.
• Collaborate closely with architecture, circuit, and verification teams.

Skills

Analog and mixed signal design

High-speed serial links

Layout optimization

Signal integrity management

Collaboration with circuit designers

Education

B. Tech/B. E in Electronics, Electronics & Communications, or VLSI Engineering

M. Tech in Electronics engineering, Microelectronics or VLSI Engineering

Job description

Roles and Responsibilities

• Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
• Execute high‑speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
• Design and optimize array‑based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi‑byte and multi‑channel configurations.
• Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.
• Drive layout‑aware co‑design with circuit designers to meet timing, noise, IR, and EM requirements for mixed‑signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.
• Apply best practices for power distribution, grounding, and isolation, including guard rings, deep‑N‑well usage, decoupling strategies, and domain separation to protect critical analog and high‑speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results to ensure silicon‑accurate performance of high‑speed and analog‑intensive LPDDR blocks.
• Support post‑layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.
• Collaborate closely with architecture, circuit, verification, and silicon debug teams to enable first‑silicon success and high‑volume manufacturability of LPDDR products.
• Contribute to PPA optimization with a strong focus on low‑power operation, area efficiency, and reliability requirements specific to LPDDR applications.
• Foster a culture of knowledge sharing and continuous improvement, contributing to VXL‑compatible layout flows, best practices, and design reviews that enable first‑silicon success.
• Leverage AI/ML knowledge as a value‑add to support data‑driven optimization, layout automation initiatives, and improved debug and correlation workflows.

Qualifications

• 6+ years of solid hands‑on experience in analog and mixed signal, high‑speed serial links.
• B. Tech/B. E in Electronics, Electronics & Communications, or VLSI Engineering.
• M. Tech in Electronics engineering, Microelectronics or VLSI Engineering.

Position: Senior AMS Layout Engineer – DPG‑LPDDR

Micron offers a range of medical, dental, vision, income protection, paid time‑off, and paid holidays to support team members' well‑being and professional growth.

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.