Staff Layout Engineer – DPG Layout

Micron Technology; Hyderabad; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Micron Technology, Inc in Hyderabad is looking for a Semiconductor Design Engineer 4 to lead the development of critical analog layouts. You will apply your extensive experience in analog layout design, leveraging AI-driven automation to improve efficiency and quality.

The ideal candidate holds a B.Tech or M.Tech in relevant fields, has over 6 years of experience, and a solid background in Cadence tools and layout techniques. This position offers a chance to innovate within a supportive and diverse workplace.

Qualifications

• 6+ years of experience in analog/custom layout design.
• Strong expertise in Cadence Virtuoso and Calibre DRC/LVS.
• Hands-on experience with memory layouts and analog layout fundamentals.

Responsibilities

• Own development and implementation of analog and mixed-signal layouts.
• Perform layout verification and drive delivery of blocks.
• Mentor engineers in layout fundamentals and best practices.

Skills

Analog layout design expertise

Cadence Virtuoso expertise

AI-driven automation

Problem-solving

Education

B.Tech in Electronics or VLSI Engineering

M.Tech in VLSI Design or Electronics Engineering

Tools

Cadence Virtuoso

Calibre DRC/LVS

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role and Responsibilities

• Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership.
• Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization.
• Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.
• Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans.
• Develop and deploy AI‑enabled methodologies for semi‑automated floorplanning, parasitic estimation, layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows.
• Demonstrate technical leadership in planning, area and cycle‑time estimation, delegation and execution.
• Guide and mentor engineers in Analog layout fundamentals, Automation‑first approach, Design‑for‑quality and design‑for‑yield practices.
• Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities.
• Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows.

Job Requirements

• 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.
• Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands‑on ownership of verification closure.
• Proven experience in layout of critical analog blocks, including but not limited to Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps, etc.
• Hands‑on experience with memory layouts, including DRAM, SRAM, CAM, OTP and understanding of array‑to‑periphery integration.
• Deep understanding of analog layout fundamentals, including Matching and symmetry, EM, latch‑up, coupling, crosstalk, IR‑drop, shielding, guard‑ring strategies, parasitic effects.
• Strong ability to interpret design intent and constraints and translate them into high‑quality, manufacturable layouts.
• Proven expertise in defining, developing, and scaling AI‑driven automation and AI‑assisted methodologies for complex layout workflows.
• Demonstrated problem‑solving skills in physical verification, debug, and layout optimization dedicated to improving yield.

Education

• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering
• M.Tech in VLSI Design, Microelectronics, or Electronics Engineering

Job Profile(s)

Semiconductor Design Engineer 4

Relocation level: (TBD)

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.