Sr AMS Layout Engineer-DPG-LPDDR

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is seeking a skilled analog and mixed signal layout designer with over 6 years of experience. The role involves designing critical components for LPDDR PHYs, ensuring signal integrity, and collaborating with circuit teams for optimal performance.

The ideal candidate holds a B. Tech in Electronics and a strong foundation in analog layout techniques, signal integrity challenges, and supports through best practices for high-speed signals. This position provides an opportunity to work at the forefront of LPDDR technology and contribute to innovative solutions.

Qualifications

• 6+ years of hands-on experience in analog and mixed signal design.
• Expertise in layout-aware co-design with circuit designers.
• Experience with DRC/LVS closure and parasitic extraction.

Responsibilities

• Own analog and mixed signal layout of critical blocks.
• Execute high-speed LPDDR interface layout addressing signal integrity.
• Design and optimize array-based layouts for DQ/DQS byte lanes.

Skills

Analog layout design

Mixed signal design

High-speed interface layout

Signal integrity

AI/ML knowledge

Education

B. Tech/B. E in Electronics

M. Tech in Electronics Engineering

Job description

Roles and Responsibilities

Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.

Execute high‑speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.

6+ years of solid hands‑on experience in analog and mixed signal, high‑speed serial links.

Design and optimize array‑based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi‑byte and multi‑channel configurations.

Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.

Drive layout‑aware co‑design with circuit designers to meet timing, noise, IR, and EM requirements for mixed‑signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.

Apply best practices for power distribution, grounding, and isolation, including guard rings, deep‑N‑well usage, decoupling strategies, and domain separation to protect critical analog and high‑speed signals.

Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results to ensure silicon‑accurate performance of high‑speed and analog‑intensive LPDDR blocks.

Support post‑layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.

Collaborate closely with architecture, circuit, verification, and silicon debug teams to enable first‑silicon success and high‑volume manufacturability of LPDDR products.

Contribute to PPA optimization with a strong focus on low‑power operation, area efficiency, and reliability requirements specific to LPDDR applications.

Foster a culture of knowledge sharing and continuous improvement, contributing to VXL‑compatible layout flows, best practices, and design reviews that enable first‑silicon success.

Leverage AI/ML knowledge as a value‑add to support data‑driven optimization, layout automation initiatives, and improved debug and correlation workflows.

Education

• B. Tech/B. E in Electronics, Electronics & Communications, or VLSI Engineering
• M. Tech in Electronics engineering, Microelectronics or VLSI Engineering

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.