Sr Layout Engineer-DPG-LPDDR

Micron Technology, Inc; Hyderabad; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Micron Technology, Inc. in Hyderabad, India is seeking a senior engineer to own the custom analog and mixed signal layout for LPDDR PHYs.

You will tackle high-speed interface layouts, ensure symmetry and matching, and collaborate with architecture, circuit, and silicon teams to enable first-silicon success. The role requires 6+ years of analog/mixed-signal layout experience, proficiency in LPDDR blocks, and the ability to drive DRC/LVS closure and post-layout optimizations for high-volume

Qualifications

• 6+ years of hands-on experience in analog and mixed-signal layouts.
• Experience with high-speed LPDDR interfaces and signal integrity.
• Ability to drive layout-aware co-design and DRC/LVS closure.

Responsibilities

• Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs.
• Execute high-speed LPDDR interface layout (LPDDRx) addressing SI challenges.
• Design and optimize array-based layouts for LPDDR DQ/DQS lanes and replica paths.
• Implement custom digital block layouts within the LPDDR PHY including training logic and calibration engines.
• Drive layout-aware co-design with circuit designers to meet timing, noise, and EM requirements.

Skills

Analog layout

Mixed-signal

LPDDR layout

High-speed links

DRAM/LPDDR

Education

B.Tech/B.E in Electronics

M.Tech in Electronics / VLSI

Tools

Calibre

Cadence Virtuoso

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Roles and Responsibilities

• Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
• Execute high-speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
• 6+ years of solid hands-on experience in analog and mixed signal, high-speed serial links.
• Design and optimize array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi-byte and multi-channel configurations.
• Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.
• Drive layout-aware co-design with circuit designers to meet timing, noise, IR, and EM requirements for mixed-signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.
• Apply best practices for power distribution, grounding, and isolation, including guard rings, deep-N-well usage, decoupling strategies, and domain separation to protect critical analog and high-speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results to ensure silicon-accurate performance of high-speed and analog-intensive LPDDR blocks.
• Support post-layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.
• Collaborate closely with architecture, circuit, verification, and silicon debug teams to enable first-silicon success and high-volume manufacturability of LPDDR products.
• Contribute to PPA optimization with a strong focus on low-power operation, area efficiency, and reliability requirements specific to LPDDR applications.
• Foster a culture of knowledge sharing and continuous improvement, contributing to VXL-compatible layout flows, best practices, and design reviews that enable first-silicon success.
• Leverage AI/ML knowledge as a value-add to support data-driven optimization, layout automation initiatives, and improved debug and correlation workflows.
• Leveraging Artificial Intelligence.

Education

• B. Tech/B. E in Electronics, Electronics & Communications, or VLSI Engineering
• M. Tech in Electronics engineering, Microelectronics or VLSI Engineering

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.