Sr AMS Layout Engineer-DPG-LPDDR

Micron Technology; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Micron Technology in Hyderabad is seeking an experienced engineer to own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs. Responsibilities include executing high-speed LPDDR interface layouts, ensuring robustness against signal integrity challenges, and collaborating closely with teams across architecture, circuit design, and silicon debug.

The ideal candidate holds a B. Tech in Electronics and has over 6 years of hands-on experience in similar roles, emphasizing DRC/LVS closure and layout optimization.

Qualifications

• 6+ years of solid hands-on experience in analog and mixed signal, high-speed serial links.
• Expertise in DRC/LVS closure, parasitic extraction, and silicon validation.

Responsibilities

• Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs.
• Execute high-speed LPDDR interface layout addressing signal integrity challenges.
• Drive layout-aware co-design with circuit designers to meet various requirements.

Skills

Analog and mixed signal design

High-speed serial links

Layout optimization

Signal integrity

Power distribution and grounding

Education

B. Tech/B. Eng. in Electronics

M. Tech in Electronics Engineering

Job description

Roles and Responsibilities

• Own the custom analog and mixed signal layout of critical analog blocks for LPDDR PHYs, including critical Datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
• Execute high-speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes.
• 6+ years of solid hands-on experience in analog and mixed signal, high-speed serial links.
• Design and optimize array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and scalability across multi-byte and multi-channel configurations.
• Implement custom digital block layouts within the LPDDR PHY, including training logic, calibration engines, and test/debug circuitry, with careful consideration of clocking, congestion, and interaction with sensitive analog regions.
• Drive layout-aware co-design with circuit designers to meet timing, noise, IR, and EM requirements for mixed-signal LPDDR blocks, incorporating parasitic awareness early in the design cycle.
• Apply best practices for power distribution, grounding, and isolation, including guard rings, deep-N-well usage, decoupling strategies, and domain separation to protect critical analog and high-speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results to ensure silicon-accurate performance of high-speed and analog-intensive LPDDR blocks.
• Support post-layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance.
• Collaborate closely with architecture, circuit, verification, and silicon debug teams to enable first-silicon success and high-volume manufacturability of LPDDR products.
• Contribute to PPA optimization with a strong focus on low-power operation, area efficiency, and reliability requirements specific to LPDDR applications.
• Foster a culture of knowledge sharing and continuous improvement, contributing to VXL-compatible layout flows, best practices, and design reviews that enable first-silicon success.
• Leverage AI/ML knowledge as a value‑add to support data-driven optimization, layout automation initiatives, and improved debug and correlation workflows.

Education

• B. Tech/B. Eng. in Electronics, Electronics & Communications, or VLSI Engineering
• M. Tech in Electronics engineering, Microelectronics or VLSI Engineering

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.