Sr. Layout Design Engineer

Mulya Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Mulya Technologies seeks a Sr. Layout Design Engineer to lead top-level chip-planning and block-level layouts for CMOS and BiCMOS circuits. You will coordinate offshore layout designers, train juniors, and contribute to standard methodologies globally.

You will review designs, perform schematic-driven layouts, ensure die-area efficiency, and verify layouts to meet DRC/LVS/ERC standards. Strong collaboration across time zones is essential.

Qualifications

• AA/AS Degree in Layout Design or related field or equivalent experience.
• 10 years’ experience with layout design for analog and full-custom digital blocks.
• Experience TSMC 180nm, 65nm, 22nm process technologies.
• Proficient in using layout editing tools in the Cadence Virtuoso design environment.
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre.
• Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation.
• Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints.
• Experience in chip‐level floor planning and analog block integration.
• Experience chip level integration, verifications, and tape-out.
• Ability to use productivity‑enhancing tools and design scripts to further automate tasks.

Responsibilities

• Remote interfacing with global design teams across time zones.
• Lead top-level chip-planning and perform block-level layouts for CMOS/BiCMOS.
• Perform schematic-driven layout and design constraints.
• Design die-area efficient layouts per circuit requirements.
• Perform floor-planning, power routing, shielding, and device-matching layout.
• Verify layouts with DRC, LVS, and ERC.
• Contribute to chip-level routing and layout needs.
• Perform chip-level integration, verifications, and tape-out.
• Train junior layout engineers and offshore contractors.
• Develop common best practices and workflow across sites.

Skills

Layout Design

Analog & Digital

Cadence Virtuoso

DRC/LVS/ERC

Tape-out

Education

AA/AS in Layout Design

Tools

Calibre

Mentor Calibre

Cadence PVS

Job description

Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to develop standard layout methodologies across site. Contribute to build process and procedures to achieve high layout quality

Responsibilities

• Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
• Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
• Perform schematic-driven layout and design constraints
• Design die-area efficient layouts according to circuit designer requirements
• Perform block or top-level layout designs
• Perform floor-planning, power line planning, shielding, and device-matching layout
• Verify layouts. Pass DRC, LVS, and ERC
• Contribute to various chip-level routing and layout needs
• Perform chip level integration, verifications, and tape-out
• Support other projects as needed by management
• Train junior layout engineers and offshore layout contractors
• Contribute to develop common best practices and workflow across all sites
• Contribute to build process and procedures to achieve high layout quality

Qualifications & Requirements

• AA/AS Degree in Layout Design or related field or equivalent experience
• 10 years’ experience with layout design for analog and full-custom digital blocks
• Experience TSMC 180nm, 65nm, 22nm process technologies
• Proficient in using layout editing tools in the Cadence Virtuoso design environment
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
• Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
• Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
• Experience in chip‐level floor planning and analog block integration
• Experience chip level integration, verifications, and tape-out
• Ability to use productivity‑enhancing tools and design scripts to further automate tasks is also desirable
• Must be able to lift, push, and pull up to 5 lbs.

Desired Characteristics & Attributes

• Attention to detail, organized, accurate and can produce efficient layout techniques
• Has a good track record of on time work delivery
• Has a self-motivated, team player with good communication skills
• Ability to work well with others in a fast-paced collaborative team environment