Layout Engineer, DEG Layout

Micron Technology, Inc; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Micron Technology, Inc is seeking a Semiconductor Design Engineer in Hyderabad, India to design and develop layouts for critical analog and mixed-signal blocks. The ideal candidate will have 3 to 7 years of experience in advanced CMOS layout design and expertise in Cadence and Mentor Graphics tools.

The role demands proactive communication with global teams and an understanding of how layout affects performance. A BE or MTech in Electronic/VLSI Engineering is required, along with excellent problem-solving abilities.

Qualifications

• 3 to 7 years of experience in analog/custom layout design in advanced CMOS processes.
• Hands-on experience creating layouts for various components like temperature sensors, PLLs, etc.
• Excellent verbal and written communication skills.

Responsibilities

• Responsible for design and development of critical analog and mixed-signal blocks.
• Perform layout verification and quality checks.
• Deliver block-level layouts on time.

Skills

Analog/custom layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Physical verification

Problem-solving

Communication skills

Education

BE or MTech in Electronic/VLSI Engineering

Job description

Role and Responsibilities

• Responsible for design and development of critical analog, mixed-signal, custom digital blocks, and full‑chip level integration support.
• Perform layout verification (LVS/DRC/antenna), quality checks and support documentation.
• Deliver block‑level layouts on time with acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, and execution to meet project milestones in a multi‑project environment.
• Contribute to effective project management.
• Communicate effectively with global engineering teams to ensure layout project success.

Qualifications

• 3 to 7 years of experience in analog/custom layout design in advanced CMOS processes across multiple technology nodes (planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS required.
• Hands‑on experience creating layouts for temperature sensors, PLLs, ADCs, DACs, LDOs, bandgap references, charge pumps, current mirrors, comparators, differential amplifiers, etc.
• Good understanding of analog‑layout fundamentals such as matching, electro‑migration, latch‑up, coupling, crosstalk, IR drop, and passive/active device parasitics.
• Understanding of how layout affects circuit performance (speed, capacitance, power, area).
• Ability to comprehend design constraints and implement high‑quality layouts.
• Understanding of design hierarchy and memory‑design architectures.
• Excellent problem‑solving skills in physical verification of custom layouts.
• Experience with multiple tape‑out support is an added advantage.
• Excellent verbal and written communication skills.
• Proactive exploration of AI‑related tools for day‑to‑day tasks.

Education

BE or MTech in Electronic/VLSI Engineering

Job Profile(s)

Semiconductor Design Engineer2

Equal Opportunity Employment Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.