Sr. Layout Design Engineer

SiTime; Bengaluru; On-site; INR 2,800,000 - 4,200,000; Full time

Job summary

SiTime is seeking a Sr Layout Design Engineer in Bengaluru to lead top‑level chip planning and block‑level custom layouts for CMOS and BiCMOS circuits. You will review offshore layout work, train juniors, and help establish standard methodologies across sites to ensure high layout quality.

The role involves coordinating global teams, performing schematic‑driven layout, and advancing tape‑out readiness with robust DRC/LVS/ERC verification.

Qualifications

• BA/BS Degree in Layout Design or related field or equivalent experience.
• 10 years of experience with layout design for analog and full‑custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm process technologies.
• Proficient in Cadence Virtuoso layout environment.
• Solid debugging with DRC/LVS/ERC using Cadence PVS or Mentor Calibre.
• Knowledge of parasitic, matching, crosstalk, latch‑up, IR drop, EM, deep N‑well and NTN isolation.
• Ability to improve device matching and power distribution within area constraints.
• Experience in chip‑level floor planning and analog block integration.
• Ability to automate tasks with scripts.

Responsibilities

• Lead top‑level chip planning and perform block‑level/custom layouts for CMOS and BiCMOS circuits.
• Coordinate offshore layout designers and train junior engineers across sites.
• Perform schematic‑driven layout and enforce design constraints.
• Design die‑area efficient layouts per circuit designer requirements.
• Lead floor planning, power distribution, shielding, and device matching layouts.
• Verify layouts by DRC, LVS, and ERC passes.
• Contribute to chip‑level routing, integration, and tape‑out.
• Develop common best practices and workflows across sites.
• Support build processes and quality improvements.

Skills

Attention to detail

Team collaboration

Communication

Problem solving

Time management

Education

BA/BS Degree in Layout Design or related field

Tools

Cadence Virtuoso

PVS

Mentor Calibre

TSMC process knowledge (180nm/65nm/22nm)

Job description

About SiTime

SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. We deliver MEMS‑based Precision Timing solutions that offer greater accuracy, smaller size and resilience, powering over 400 applications worldwide.

Job Summary

The Sr. Layout Design Engineer will lead top‑level chip‑planning and perform block‑level custom layouts for CMOS and BiCMOS circuits. The engineer will review and coordinate the work performed by offshore layout designers, train junior layout engineers and offshore contractors, contribute to standard layout methodologies across sites, and develop processes and procedures to achieve high layout quality.

Responsibilities

• Require remote interfacing with local and global design and layout teams in multiple design centers across different time zones
• Lead top‑level chip‑planning and perform functional‑block‑level, block‑level, sub‑block level, leaf cell, and standard cell custom layouts for CMOS and BiCMOS circuits
• Perform schematic‑driven layout and design constraints
• Design die‑area efficient layouts according to circuit designer requirements
• Perform block or top‑level layout designs
• Perform floor‑planning, power line planning, shielding, and device‑matching layout
• Verify layouts by passing DRC, LVS, and ERC
• Contribute to various chip‑level routing and layout needs
• Perform chip level integration, verifications, and tape‑out
• Support other projects as needed by management
• Train junior layout engineers and offshore layout contractors
• Contribute to developing common best practices and workflow across all sites
• Contribute to build process and procedures to achieve high layout quality

Qualifications & Requirements

• BA/BS Degree in Layout Design or related field or equivalent experience
• 10 years of experience with layout design for analog and full‑custom digital blocks
• Experience with TSMC 180nm, 65nm, 22nm process technologies
• Proficient in using layout editing tools in the Cadence Virtuoso design environment
• Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
• Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor‑layout dependent effects, latch‑up, IR drop, electro‑migration (EM), and deep N‑well and NTN isolation
• Strong capability of solving device matching, electro‑migration, signal integrity and power distribution problems while meeting area constraints
• Experience in chip‑level floor planning and analog block integration
• Experience in chip level integration, verifications, and tape‑out
• Ability to use productivity‑enhancing tools and design scripts to further automate tasks is also desirable
• Must be able to lift, push, and pull up to 5 lbs

Desired Characteristics & Attributes

• Attention to detail, organized, accurate and can produce efficient layout techniques
• Has a good track record of on‑time work delivery
• Has a self‑motivated, team player with good communication skills
• Ability to work well with others in a fast‑paced collaborative team environment

Compensation Range

SiTime offers a comprehensive and highly competitive compensation package designed to attract top talent. In addition to a base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals. Equity grants are also provided, offering a meaningful opportunity to share in the company’s future growth and success.

Equal Opportunity Employment

SiTime is an Equal Opportunity Employer. We treat each person fairly and do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status. SiTime participates in the E‑Verify program.