SR ENGINEER, HIG HBM LAYOUT

Micron Technology; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Micron Technology, Inc in Hyderabad is seeking a SR ENGINEER, HIGH HBM LAYOUT to design and develop critical analog and mixed-signal layouts. Candidates should have 6 to 9 years of experience in memory/custom layout design with a strong background in advanced CMOS processes.

The role involves layout verification, project management, and guiding junior team members. A BE or MTech in Electronic/VLSI Engineering is required.

Applicants will be considered without regard to race, color, religion, or other statuses.

Qualifications

• 6 to 9 years of experience in memory/custom layout design in advanced CMOS processes.
• Hands-on experience creating layouts for critical blocks like temperature sensor, PLL, ADC, DAC.
• Strong understanding of matching, electro-migration, latch-up, coupling, crosstalk, and IR-drop.

Responsibilities

• Design and develop critical analog, mixed-signal, custom digital blocks.
• Perform detailed layout verification including LVS, DRC, and quality control.
• Plan, estimate, schedule, delegate and execute tasks for project milestones.

Skills

Memory/custom layout design

Cadence Virtuoso

Mentor Graphics Calibre

Analog layout fundamentals

Problem-solving skills

Education

BE or MTech in Electronic/VLSI Engineering

Job description

SR ENGINEER, HIGH HBM LAYOUT – Micron Technology, Hyderabad, India

Role and Responsibilities

• Design and develop critical analog, mixed‑signal, custom digital blocks and provide full‑chip level integration support.
• Perform detailed layout verification (LVS/DRC/antenna checks), quality control and documentation.
• Deliver block‑level layouts on schedule with acceptable quality.
• Plan, estimate area/time, schedule, delegate and execute tasks to meet project milestones in a multi‑project environment.
• Guide junior team members on sub‑block layout execution and review their work.
• Contribute to effective project‑management and communicate with global engineering teams to ensure project success.

Qualifications and Requirements

• 6 to 9 years of experience in memory/custom layout design in advanced CMOS processes (planar, FinFET) across various technology nodes.
• Expertise in Cadence Virtuoso and Mentor Graphics Calibre for DRC/LVS.
• Hands‑on experience creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, charge pump, current mirrors, comparators and differential amplifiers.
• Strong understanding of analog layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, parasitics).
• Knowledge of how layout affects circuit performance (speed, capacitance, power, area).
• Ability to interpret design constraints, implement high‑quality layouts, and support multi‑tape‑out processes.
• Excellent problem‑solving, written and verbal communication skills.

Education

BE or MTech in Electronic/VLSI Engineering.

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.