Principal Engineer- HIG HBM Layout

Micron Technology; Hyderabad; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

Micron Technology in Hyderabad seeks a seasoned layout engineer to lead the end-to-end layout execution of analog and mixed-signal products. You will mentor a team, ensuring quality project delivery while collaborating across global teams.

The ideal candidate has 15+ years of experience in CMOS processes and a strong background in team leadership and communication. Join a dynamic team to drive innovation and ensure top performance in the industry.

Qualifications

• 15+ years of experience in analog/custom layout in advanced CMOS process.
• Minimum 4+ years developing teams and project experience.
• Strong skills in layout and floor planning, manual routing.

Responsibilities

• Lead layout execution for analog and mixed-signal blocks for HBM products.
• Drive project planning, scheduling, and milestone tracking.
• Mentor junior engineers, conduct design reviews.

Skills

Layout Design

Team Leadership

Project Management

Communication Skills

Analog/Mixed-Signal Expertise

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Calibre DRC/LVS

Job description

Role And Responsibilities

• Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and full‑chip integration for HBM products.
• Own full‑chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA).
• Technical Expertise: Hands‑on experience in layout design of critical Memory/Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic, IOs, PLLs, ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers.
• Drive project planning and execution, including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs.
• Ensure timely delivery with quality, responsible for block‑level and full‑chip layouts meeting schedule commitments and quality expectations.
• Perform and oversee layout verification activities including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits.
• Lead and mentor the layout team, guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development.
• Drive innovation and productivity improvements, including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality.
• Collaborate with global cross‑functional teams (Design, Verification, IP, Packaging) and ensure strong communication for project alignment and success.
• Support customer and product integration needs, including specification alignment, design clarifications, and successful implementation of Micron solutions.
• Contribute to organizational growth and leadership initiatives, including team building, hiring, performance management, and representing Micron in industry engagements.

Qualification / Requirements

• 15+ years experience in analog/custom layout in advanced CMOS process.
• Minimum 4+ years developing teams and project experience.
• Should have experience in leading multiple project and Tape‑out.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Must have strong skills in layout and floor planning skills and manual routing.
• Strong ability to build, and continuously develop a premier analog/mixed‑signal layout team.
• Experienced in running multiple Custom IC layout projects.
• Excellent verbal and written communication skills required.
• Capable of working in a multi-functional, multi-site team environment in multiple time zones.

Education

BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.