STAFF ENG-HBM-LAYOUT

Micron Technology; Hyderabad; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Micron Technology in Hyderabad, India seeks a Layout Design Engineer to drive analog/custom layout for high bandwidth memory projects. You will design critical blocks, perform full chip integration, and coordinate with global teams to meet milestones.

The role requires 8–15 years in CMOS layout, hands-on experience with Cadence VLE/VXL and Mentor Calibre, and a BE/MTech in Electronic/VLSI. Excellent communication and leadership skills are essential.

Qualifications

• 8 to 15 years of experience in analog/custom layout design in advanced CMOS processes.
• Experience with multiple technology nodes (Planar, FinFET).
• Hands-on layout experience with blocks like sensors, PLLs, ADCs, DACs, LDOs, Bandgaps.

Responsibilities

• Design and development of critical layout and co-optimization objectives.
• Tapeout PWF reticles and full chip layout integration.
• Collaborate with Scribe Design and HBM teams across global sites.
• Perform LVS/DRC/Antenna checks and ensure on-time delivery of block layouts.
• Guide junior team members and contribute to project management and communication.

Skills

Analog layout

Cadence VLE/VXL

Mentor Calibre

Full chip verification

AI-assisted design

Layout fundamentals

Team leadership

Tapeouts

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence

Mentor Graphics Calibre

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

We are looking for a Layout Design Engineer for Micron Technology’s HBM Team in Hyderabad, India. In this role you will work on intensive applications such as artificial intelligence and high-performance computing solutions, High Bandwidth Memory, collaborating with peer teams across Micron’s global footprint in a multiple project‑based environment.

Responsibilities

• Responsible for Design and development of critical Design and Co‑optimization objectives, mixed‑signal, custom digital block and full chip level integration support.
• Build and tapeout PWF Reticles Design.
• Engage with Scribe Design team to capture Advanced Packaging requirements and Review.
• TSV design engagement with HIG‑HBM DTPCO teams (electrical, thermal and mechanical performance).
• Creation and Maintenance of DFMEA related to advanced packaging process steps like PWF, die stacking etc.
• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Guide junior team‑members in their execution of Sub block‑level layouts & review their work.
• Contribute to effective project‑management.
• Effectively communicate with Global engineering teams to assure the success of layout project.

Qualifications

• 8 to 15 years’ experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Hands‑on experience creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc.
• Hands‑on experience in Reticle development and Full Chip Verification.
• Hands‑on capability to automate or use AI features for fast and efficient project execution.
• Good understanding of Layout fundamentals (e.g., Matching, Electro‑migration, Latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices).
• Understanding layout effects on the circuit such as speed, capacitance, power and area.
• Excellent command and problem‑solving skills in physical verification of custom layout.
• Multiple Tape out support experience will be an added advantage.
• Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development.
• Excellent verbal and written communication skills.

Education: BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.