Engineer, HIG HBM Layout

Micron Technology, Inc; Hyderabad; Vor Ort; INR 800.000 - 1.200.000; Vollzeit

Zusammenfassung

Micron Technology, Inc is seeking a Layout Design Engineer for its HBM Team in Hyderabad, India. This role emphasizes designing critical analog, mixed-signal, and custom digital blocks, along with offering full chip level integration support.

The ideal candidate should possess 2–4 years of experience in memory/custom layout design, proficiency in Cadence and Mentor Graphics tools, and strong communication skills. This position promises a dynamic work environment with opportunities to guide junior colleagues and manage multiple projects.

Qualifikationen

• 2–4 years of experience in memory/custom layout design in advanced CMOS process.
• Hands-on experience creating layout of critical blocks such as temperature sensor, PLL, ADC, etc.
• Excellent verbal and written communication skills.

Aufgaben

• Responsible for design and development of critical analog, mixed-signal, and custom digital blocks.
• Perform layout verification such as LVS/DRC/Antenna, quality check and documentation.
• Guide junior team-members in execution of sub-block-level layouts.

Kenntnisse

Memory/custom layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Problem-solving skills

Ausbildung

BE or MTech in Electronic/VLSI Engineering

Jobbeschreibung

We are looking for a Layout Design Engineer for Micron Technology’s HBM Team in Hyderabad, India. The role focuses on designing critical analog, mixed‑signal, custom digital blocks and supporting full chip level integration for high-performance computing solutions.

Role and Responsibilities

• Responsible for design and development of critical analog, mixed‑signal, custom digital block and full chip level integration support.
• Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design.
• Perform layout verification such as LVS/DRC/Antenna, quality check and documentation.
• Responsible for on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Guide junior team‑members in execution of sub‑block‑level layouts and review their work.
• Contribute to effective project‑management.
• Effectively communicate with global engineering teams to assure the success of layout project.

Qualifications

• 2–4 years of experience in memory/custom layout design in advanced CMOS process at various technology nodes (Planar, FinFET).
• Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands‑on experience creating layout of critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Good understanding of analog layout fundamentals (matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, device parasitics).
• Understanding of how layout effects circuit performance such as speed, capacitance, power and area.
• Ability to understand design constraints and implement high‑quality layouts.
• Ability to understand design hierarchy and different architectures for memory designs.
• Excellent problem‑solving skills in physical verification of custom layout.
• Multiple tape‑out support experience a plus.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronic/VLSI Engineering.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.