Senior RTL Integration Engineer

HappieHire; Bengaluru; On-site; INR 2,200,000 - 3,400,000; Full time

Benefits offered by this job

On-site

Job summary

HappieHire in Bengaluru, Karnataka, invites an experienced RTL Integration Engineer to lead SoC integration for next‑gen semiconductor products. You will integrate multi‑IP blocks, manage AMBA interconnects, and work with cross‑functional teams to ensure clean handoffs and tapeout readiness.

The ideal candidate has 7+ years of hands‑on RTL experience, deep SystemVerilog/Verilog knowledge, and a strong background in static sign‑off, timing constraints, and automation using Python/TCL/Perl.

Qualifications

• 7+ years of hands-on RTL integration in the VLSI/Semiconductor industry.
• Strong knowledge of SystemVerilog/Verilog and digital design principles.
• Experience with static sign-off checks (Lint, CDC, RDC, UPF/CPF low-power).

Responsibilities

• Integrate multi‑million gate SoCs, subsystems, and third‑party IPs using SystemVerilog/Verilog.
• Configure and assemble chip interconnect fabrics using AMBA protocols (AXI4, AHB, APB, CHI).
• Own static verification flows, including Lint, CDC, RDC, and UPF-based checks.
• Develop and maintain top-level timing constraints (SDC) and coordinate with PD and Synthesis teams.
• Drive functional and timing ECOs late in the execution cycle.
• Build RTL build systems and automated integration flows using Python, TCL, Perl, or Shell.
• Mentor junior engineers and collaborate with Verification, DFT, and Architecture teams.

Skills

SystemVerilog

AMBA protocols

RTL integration

Scripting: Python/TCL/Perl

Static sign-off

Timing constraints

SoC design

Tapeout experience

Education

BE/B.Tech/M.E./M.Tech in Electrical/Electronics/VLSI

Tools

SpyGlass

Questa CDC

VC-SpyGlass

Job description

Work Model: 5 Days Work from Office (On-site)

Notice Period: 30 to 60 Days

Position Overview

We are seeking a high-caliber RTL Integration Engineer with 7+ years of experience to lead SoC and subsystem integration for next-generation semiconductor products. You will be responsible for integrating complex internal/third-party IPs, managing bus fabrics, running static quality checks, and collaborating with cross-functional teams to ensure high-quality design handoffs.

Key Responsibilities

• Integrate multi-million gate SoCs, sub-systems, and third-party IPs (e.g., PCIe, DDR, Ethernet, ARM/RISC-V cores) using SystemVerilog and Verilog.
• Configure and assemble chip interconnect fabrics using AMBA bus protocols (AXI, AHB, APB, CHI).
• Own and execute static verification flows, including Linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and UPF-based low-power intent checks (using tools like SpyGlass, Questa CDC, or VC-SpyGlass).
• Develop and maintain top-level timing constraints (SDC) and work closely with Physical Design (PD) and Synthesis teams to resolve timing, area, and power issues.
• Drive functional and timing ECOs late in the execution cycle.
• Build, maintain, and optimize RTL build systems and automated integration flows using Python, TCL, Perl, or Shell scripting.
• Mentor junior engineers and collaborate with Verification, DFT, and Architecture teams to define integration specs and debug full-chip issues.

Required Qualifications & Skills

• Education: B.E./B.Tech/M.E./M.Tech in Electrical/Electronics Engineering, VLSI, or related disciplines.
• Experience: 7+ years of hands-on experience in SoC/Subsystem RTL integration within the VLSI/Semiconductor industry.
• Core Technical Expertise:
• Advanced knowledge of SystemVerilog/Verilog and digital design principles.
• In-depth understanding of AMBA protocols (AXI4, AHB, APB, CHI) and memory controller/interconnect architecture.
• Proven track record running static sign-off checks (Lint, CDC, RDC, UPF/CPF low-power intent).
• Solid understanding of logical synthesis, SDC timing constraints, and physical design interfaces.
• Automation: Strong proficiency in scripting using Python, TCL, or Perl for workflow automation.
• Key Attributes: Strong diagnostic and problem-solving skills, with a track record of driving complex designs through tapeout.