RTL Design Engineer

Clarus Advisers; Hyderabad; Presencial; INR 1.200.000 - 1.800.000; Jornada completa

Descripción de la vacante

Clarus Advisers is seeking an RTL Design Engineer/Senior Engineer to drive SOC assembly and chip-level functions. The role requires handling front-end design quality checks and coordinating with multi-functional teams to ensure timely SOC milestones.

Candidates should have 4+ years in chip design, strong Verilog RTL experience, and solid scripting skills in Perl/Python to support design automation and cross-functional workflows.

Formación

• 4+ years of proven experience in chip design, specializing in SOC integration and design automation.
• Padring and fuse/floorsweep design experience is a bonus.
• Experience in RTL design (Verilog), System-On-Chip design/implementation flow.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Exposure to various Chip Design Functions to collaborate and solve complex multi-functional problems.
• Background in SOC Verification, Synthesis, Physical design and DFT is a bonus.
• Experience in RTL Build flows and Makefiles is a plus.
• Excellent analytical and problem-solving skills.

Responsabilidades

• Drive SOC Assembly and design chip level functions for SOCs.
• Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.
• Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.
• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
• Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them.

Conocimientos

RTL design

SoC integration

Verilog

Scripting (Perl/Python)

Problem solving

Herramientas

Makefiles

Descripción del empleo

Company Overview

Our client is a Semiconductor MNC

Position Overview

RTL Design Engineer/Senior Engineer

Responsibilities

• Drive SOC Assembly and design chip level functions for SOCs.
• Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.
• Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.
• Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
• Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them.

Skills & Experience

• 4+ years of proven experience in chip design, specializing in SOC integration and design automation. Padring and fuse/floorsweep design experience is a bonus.
• Experience in RTL design (Verilog), System-On-Chip design/implementation flow.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Exposure to various Chip Design Functions to be able to collaborate and solve complex multi-functional problems.
• Background in SOC Verification, Synthesis, Physical design and DFT is a bonus.
• Experience in RTL Build flows and Makefiles is a plus.
• Excellent analytical and problem-solving skills.