Chip top level RTL integration lead

HCLTech; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

HCLTech in Bengaluru seeks a senior RTL integration lead to own the top-level SoC integration, aligning architecture, design, verification, and physical teams for tapeout. You will integrate multiple IPs, ensure clean connectivity, and deliver synthesis-ready RTL.

You will drive quality checks (SpyGlass, CDC/RDC), mentor RTL engineers, and coordinate with DV/DFT/PD teams to enable system-level bring-up across domains.

Qualifications

• 12–18+ years in RTL design/integration.
• Experience leading SoC integration ownership.
• Strong coordination across large teams.

Responsibilities

• Own top-level RTL integration of SoC and ensure synthesis-ready RTL.
• Interface & connectivity management across IPs, NoC/bus, and interconnects.
• Drive RTL quality checks (Lint, CDC/RDC) and system-level bring-up support.

Skills

RTL integration

SoC architecture

Cross-team coordination

System-level thinking

Debugging mindset

Tools

SpyGlass

Questa Lint

Design Compiler

Genus

Git / Perforce

Job description

Lead and own SoC RTL integration for complex chips, ensuring seamless assembly of multiple IPs/subsystems into a functionally correct, synthesis-ready top-level design. This role is central to aligning architecture, design, verification, and physical teams for successful tapeout.

Own top-level RTL integration of SoC:

• Integrate multiple IPs, subsystems, and third-party blocks
• Ensure clean connectivity, hierarchy, and modular structure
• Deliver synthesis-ready, lint-clean, and CDC-clean RTL

Work closely with architecture teams to:

• Translate SoC architecture into RTL structure
• Ensure correct implementation of:
  • Interconnects (NoC / bus-based)
  • Address maps
  • Reset and clock architecture

Interface & Connectivity Management

• Define and validate:
  • IP interfaces and protocols (AXI, AHB, APB, etc.)
  • Address decoding and interconnect connectivity
  • Interface mismatches
  • Integration conflicts across teams
• Define and integrate:
  • Clocking architecture (multiple clock domains)
  • Reset strategies (global/local resets)
• Ensure:
  • Clean CDC/RDC implementation

Quality & Signoff Readiness

• Drive RTL quality checks:
  • Lint (SpyGlass, Lint tools)
  • CDC/RDC analysis
  • Basic synthesis checks
• Ensure RTL is:
  • DV-ready
  • DFT-ready
  • PD-friendly
• Interface with:
  • IP/RTL design teams
  • DV teams (for testbench integration support)
  • DFT teams (for scan/test readiness)
  • PD/STA teams (for implementation alignment)
• Act as central integration point across all domains
• Integration bugs
• Boot-up and reset sequence issues
• Connectivity and functional mismatches
• Support system-level bring-up in simulation/emulation

Develop scripts/tools for:

• RTL stitching
• Connectivity checks
• Build and regression flows
• Improve integration efficiency and repeatability
• Lead and mentor RTL integration engineers
• Drive integration schedules, milestones, and reviews
• Act as owner of top-level RTL quality and readiness

Strong expertise in:

• SoC integration and architecture

Deep understanding of:

• Experience with:

  • Lint, CDC/RDC tools
  • Synthesis awareness
  • 12-18+ years in RTL design/integration
  • Chip-level RTL integration ownership
  • Lint: SpyGlass / Questa Lint
  • CDC: SpyGlass CDC / Questa CDC
  • Synthesis: Design Compiler / Genus (basic awareness)
  • Version control: Git/Perforce
  • Strong system-level thinking
  • Excellent coordination across large teams
  • Problem-solving and debugging mindset

Good to Have

• Experience in:

  • NoC-based SoC architectures
  • Emulation/FPGA bring-up

• Scripting:

  • Python / TCL / Perl
• Clean, integration-ready RTL (lint/CDC clean)
• Smooth handoff to DV, DFT, and PD teams
• Minimal integration bugs at system level