RTL Design Engineer

TekPillar®; Bengaluru Urban; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading technology company in Bengaluru is seeking a skilled RTL Design Engineer with 3–8 years of experience. The successful candidate will be responsible for micro-architecture development, RTL coding, and collaborating with verification and physical design teams. Ideal candidates should have strong skills in Verilog/SystemVerilog and experience with tools like Synopsys/Cadence. Join us to deliver high-quality silicon in an innovative environment.

Qualifications

• 3–8 years of experience in RTL Design.
• Strong experience in RTL coding for complex IP/SoC blocks.
• Experience with lint, CDC, and STA basics.

Responsibilities

• Perform micro-architecture design based on functional specifications.
• Collaborate with the verification team for testbench support and debug.
• Analyze and resolve design issues during simulation and silicon bring-up.

Skills

Verilog / SystemVerilog

Digital design fundamentals

Debugging and problem-solving

Tools

Synopsys

Cadence (VCS, Design Compiler, Genus)

Job description

We are looking for a highly skilled RTL Design Engineer with 3–8 years of hands-on experience in digital design and RTL development. The ideal candidate will be responsible for micro-architecture development, RTL coding, and working closely with verification, synthesis, and physical design teams to deliver high-quality silicon.

Responsibilities

• Perform micro-architecture design based on functional specifications.
• Collaborate with verification team for testbench support and debug.
• Perform lint, CDC, and synthesis checks.
• Analyze and resolve design issues during simulation and silicon bring-up.
• Work closely with physical design and DFT teams.
• Participate in design reviews and documentation.

Qualifications

• Should have 3-8 Years of experience in RTL Design.
• Strong experience in Verilog / SystemVerilog.
• Good understanding of digital design fundamentals.
• Experience in RTL coding for complex IP/SoC blocks.
• Hands-on with tools like Synopsys / Cadence (VCS, Design Compiler, Genus etc.).
• Experience in Lint, CDC, STA basics.
• Understanding of low power design concepts is a plus.
• Good debugging and problem-solving skills.

Preferred

• Experience in ASIC design flow.
• Exposure to AMBA protocols (AXI/AHB/APB).
• Experience in high-speed interfaces or processor-based designs.