Lead/Staff RTL Design Engineer

Silicon Labs; Hyderabad; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Silicon Labs in Hyderabad seeks an experienced RTL Design Engineer with 5–15 years in digital design and IP development to drive complex IP from spec to tape-out.

You will work on Verilog/SystemVerilog RTL, AMBA protocols (AXI/AHB/APB), and integrate IP with SoC teams, optimizing for performance, power and area.

The role requires strong debugging, synthesis/timing analysis skills and collaboration in a fast-moving, innovation-led environment.

Qualifications

• Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
• 5–15 years of experience in RTL design and digital IP development.
• Strong proficiency in Verilog/SystemVerilog.
• Solid understanding of FSM and datapath design.
• Pipelining and performance optimization.
• Clock domain crossing (CDC) and reset domain crossing (RDC).
• Experience with synthesis and timing analysis.
• Strong RTL and gate-level debugging skills.
• Familiarity with industry-standard EDA tools (Synopsys/Cadence/Mentor).
• Experience with AMBA protocols (AXI/AHB/APB).

Responsibilities

• Drive IP development from specification to tape-out.
• Ensure designs meet performance, power, and area (PPA) targets.
• Collaborate with verification teams to develop test plans and debug functional issues.
• Support synthesis, lint, CDC/RDC, and timing closure activities.
• Work closely with SoC integration teams for IP integration and bring-up.
• Support post-silicon validation and debug.
• Contribute to IP reuse, configurability, and design methodology improvements.

Skills

RTL design

Verilog/SystemVerilog

AMBA protocols

IP development

PPA optimization

Debugging

Education

Bachelor’s or Master’s degree in Electronics/Electrical Engineering

Tools

Synopsys

Cadence

Mentor

Job description

We are seeking an experienced RTL Design Engineer with 5–15 years of hands‑on experience in digital design and IP development. The ideal candidate will have strong expertise in RTL architecture and micro‑architecture definition, with experience developing reusable IP for SoC integration.

Exposure to wireless systems (preferably Wi‑Fi) and communication/peripheral IP such as SPI, UART, I2C, DMA, etc., is highly desirable.

Key Responsibilities

• Drive IP development from specification to tape‑out.
• Ensure designs meet performance, power, and area (PPA) targets.
• Collaborate with verification teams to develop test plans and debug functional issues.
• Support synthesis, lint, CDC/RDC, and timing closure activities.
• Work closely with SoC integration teams for IP integration and bring‑up.
• Support post‑silicon validation and debug.
• Contribute to IP reuse, configurability, and design methodology improvements.

Required Qualifications

• Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
• 5–15 years of experience in RTL design and digital IP development.
• Strong proficiency in Verilog/SystemVerilog.
• Solid understanding of:
• FSM and datapath design
• Pipelining and performance optimization
• Clock domain crossing (CDC) and reset domain crossing (RDC)
• Experience with synthesis and timing analysis.
• Strong RTL and gate‑level debugging skills.
• Familiarity with industry‑standard EDA tools (Synopsys/Cadence/Mentor).
• Experience with AMBA protocols (AXI/AHB/APB).

Preferred Experience

• Experience developing communication or peripheral IP such as:
• SPI, UART, I2C/I3C
• DMA controllers
• Timers, interrupt controllers
• Memory controllers
• Exposure to wireless subsystems, preferably Wi‑Fi (IEEE 802.11) architecture or MAC-level understanding.
• Experience with packet processing or high‑speed data path design.
• Exposure to security/crypto IP is a plus.
• Scripting knowledge (Python/Perl/TCL).
• Experience in advanced technology nodes is an advantage.

Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making

Not only will you be joining a highly skilled and tight‑knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.