RTL Design Engineer

Luxoft; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Luxoft is seeking an experienced RTL designer to develop synthesizable RTL in Verilog/SystemVerilog and drive IP/subsystem integration. You will ensure design readiness through linting, CDC/RDC checks, synthesis, and handoff validation.

You will own RTL reviews, fix violations, and coordinate with architecture, design, and verification teams to achieve first-pass silicon readiness. This role emphasizes automation and quality metrics to improve development throughput.

Qualifications

• 3-6 years of experience developing synthesizable RTL in Verilog/SystemVerilog.
• Translate architecture specs into scalable microarchitectures with IP integration including AXI interfaces.
• Own lint, CDC/RDC, and synthesis issue closure and signoff readiness.

Responsibilities

• Own RTL development from architecture interpretation through design handoff and IP integration.
• Perform detailed RTL reviews and quality assessments, driving closure of issues.
• Resolve Lint, CDC/RDC, X-propagation, and synthesis violations; ensure protocol compliance.
• Build and enhance design automation, dashboards, and quality gates for team-wide RTL quality.

Skills

Verilog/SystemVerilog

IP integration

AXI4/AXI4-Lite/ARB

Lint / CDC / RDC

Synthesis

Design signoff

Automation & dashboards

Tools

AMBA interfaces

Job description

Project description

The ideal candidate will develop high-quality RTL, drive IP/subsystem integration, and ensure design readiness through rigorous quality checks including Lint, CDC, RDC, synthesis, and handoff validation.

Responsibilities

• * Own RTL development from architecture interpretation through design handoff, including IP integration, clock/reset handling, address mapping, and configuration.* Perform detailed RTL reviews and quality assessments, identifying and driving closure of functional, structural, and methodology issues.* Analyze and resolve Lint, CDC/RDC, X-propagation, synthesis, and structural violations, collaborating with architecture, design, and verification teams.* Ensure RTL handoff readiness through clean signoffs, protocol compliance, register-spec alignment, and clock/reset architecture validation.* Build and enhance design automation and quality methodologies, including automated checks, regression analysis, dashboards, and team-level quality gates.

SKILLS

Must have

• * Experience: 3-6 years* Develop synthesizable RTL using Verilog/System Verilog for complex digital IPs and SoC subsystems.* Translate architecture specifications into scalable microarchitectures, integrating IPs and AMBA interfaces including AXI4, AXI4-Lite, AHB, and APB.* Drive RTL quality and design signoff, ensuring coding standards, methodology compliance, clean reviews, and first-pass silicon readiness.* Own closure of Lint, CDC, RDC, X-propagation, structural checks, synthesis issues, and design-rule violations.* Develop automation, dashboards, and quality metrics to improve RTL development, verification handoff, and signoff efficiency.

Nice to have

Candidates should be passionate about design quality, automation, and delivering production-ready RTL with minimal debug cycles.