System-on-Chip Design Engineer

leadIC Design Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

leadIC Design Pvt Ltd in Bengaluru is seeking SoC design engineers to own RTL integration and front-end signoff for complex chips. You will integrate IPs at subsystem and top level, drive Lint, CDC, RDC, and low-power checks to closure for tapeout.

You will collaborate with verification, DFT, STA and physical design teams, write UPF and SDC constraints, and improve timing, area and power QoR through synthesis. BE/BTech/ME/MTech in ECE/EEE/VLSI preferred.

Qualifications

• Strong Verilog/SystemVerilog RTL design.
• Hands-on experience with Lint, CDC, RDC, VCLP/UPF, and synthesis.
• Good understanding of clocking, reset architecture and low-power design concepts.
• SDC constraints and UPF knowledge.

Responsibilities

• SoC integration: Integrate IPs at subsystem and top level, including clock, reset, memory, pad/IO and interconnect.
• Lint: Run Lint checks, analyze violations, drive fixes with IP owners, and manage waivers to signoff.
• CDC/RDC: Set up constraints, and analyze synchronizers, reconvergence, glitches and reset domain crossings. Deliver clean signoff reports.
• Low power (VCLP): Write and review UPF. Verify isolation, level shifters, retention and power switches using static low-power checks.
• Synthesis: Write SDC constraints, run synthesis, and improve timing, area and power QoR. Run logic equivalence checks (RTL vs netlist).
• Collaboration: Work with verification, DFT, STA and physical design teams through tapeout.

Skills

Verilog/SystemVerilog RTL design

Lint/CDC/RDC/VCLP

SoC integration

Clocking/reset architecture

Scripting (Tcl/Python/Perl)

Education

BE/BTech/ME/MTech in ECE/EEE/VLSI

Tools

SpyGlass

Questa CDC

Meridian CDC

Conformal LP

UPF

Design Compiler

Fusion Compiler

Genus

Formality

Conformal LEC

Job description

We are looking for SoC design engineers to own RTL integration and front-end signoff for complex SoCs. You will integrate IPs at subsystem and top level, and drive Lint, CDC, RDC, low-power (VCLP) and synthesis checks to closure for tapeout.

Key Responsibilities

• SoC integration: Integrate IPs at subsystem and top level, including clock, reset, memory, pad/IO and interconnect. Build and maintain top-level RTL and connectivity.
• Lint: Run Lint checks, analyze violations, drive fixes with IP owners, and manage waivers to signoff.
• CDC/RDC: Set up constraints, and analyze synchronizers, reconvergence, glitches and reset domain crossings. Deliver clean signoff reports.
• Low power (VCLP): Write and review UPF. Verify isolation, level shifters, retention and power switches using static low-power checks.
• Synthesis: Write SDC constraints, run synthesis, and improve timing, area and power QoR. Run logic equivalence checks (RTL vs netlist).
• Collaboration: Work with verification, DFT, STA and physical design teams through tapeout.

Must-Have Skills

• Strong Verilog/SystemVerilog RTL design and debug.
• Hands-on experience with at least three of: Lint, CDC, RDC, VCLP/UPF, synthesis, SoC integration.
• Good understanding of clocking, reset architecture and low-power design concepts.
• SDC constraints and UPF knowledge.
• Scripting in Tcl, Python or Perl, plus Makefile-based flows.

Good to Have

• Full-cycle tapeout experience.
• ARM-based SoC and AMBA protocols (AXI/AHB/APB).
• Exposure to DFT, STA (PrimeTime) or LEC flows.
• Education: BE/BTech/ME/MTech in ECE, EEE, VLSI or a related field.
• Screening keywords for TA: VC SpyGlass, SpyGlass Lint/CDC/RDC, Questa CDC, Meridian CDC/RDC, VC LP, VCLP, Conformal LP, UPF, CPF, Design Compiler, Fusion Compiler, Genus, Formality, Conformal LEC, SDC, SoC integration