Senior RTL Integration Engineer

Weekday AI (YC W21); Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Weekday AI (YC W21) Bengaluru seeks an experienced Senior RTL Integration Engineer to lead RTL integration of complex SoCs and third-party IPs. You will work with Architecture, Design Verification, Synthesis, and Physical Design teams to deliver silicon-ready designs.

The role requires hands-on RTL integration and Verilog/SystemVerilog expertise, strong understanding of AMBA AXI4/AHB/APB, PCIe, DDR, Ethernet, and clock/reset concepts, and experience guiding tapeout-ready flows across the design

Qualifications

• 7+ years of experience in RTL design or semiconductor product development.
• Hands-on RTL integration experience with Verilog/SystemVerilog.
• Strong understanding of digital design, RTL coding, module hierarchy, and SoC architecture.

Responsibilities

• Lead RTL integration for complex SoCs, subsystems, and multi-million-gate designs.
• Integrate internal and third-party IPs using Verilog/SystemVerilog and established integration methodologies.
• Develop and maintain RTL connectivity between processors, memories, interconnects, peripherals, and subsystem interfaces.
• Work with AMBA protocols including AXI4, AHB, and APB.
• Collaborate with Architecture, Design Verification, DFT, Synthesis, Physical Design, and other teams to deliver silicon-ready designs.

Skills

RTL Integration

Verilog SystemVerilog

AMBA AXI4 AHB APB

SoC Integration

PCIe

DDR

Ethernet

ARM RISC-V

Clock and Reset

Lint CDC RDC

Scripting Python TCL

Mentoring

Education

Bachelors in Electrical Engineering

Masters in EE or related field

Tools

SpyGlass

Questa CDC

VC SpyGlass

Job description

Job Description:

This role is for one of the Weekdays clients

Salary range: Rs 2500000 - Rs 4000000 (ie INR 25-40 LPA)

Experience: 7+ yrs

Location: Bengaluru, Karnataka

Job Type: Full-time

We are looking foran experiencedSeniorRTL Integration Engineerto leadthe integration of complex RTL designs and third-party IPs for advancedSoC and semiconductor products. Thisrole requires stronghands-on expertise inRTL Integration and Verilog, along with a solid understanding of digital design, SoC architecture, interconnects, clocking, resets, and design-quality methodologies.

The ideal candidatewill be responsible for integratinglarge and complex RTL blocks, ensuring connectivity and functionality, resolving integration issues, and supporting the design through verification, synthesis, physical design, and tapeout. You will collaborate closely with Architecture, Design Verification, DFT, Synthesis, Physical Design, and other engineering teams to deliver high-quality silicon-ready designs.

KEY RESPONSIBILITIES

• LeadRTL integrationfor complex SoCs, subsystems, andmulti-million-gatedesigns.


• Integrate internal andthird-party IPsusingVerilog/SystemVerilogand established integration methodologies.


• Develop and maintain RTL connectivity between processors, memories, interconnects, peripherals, and subsystem interfaces.


• Work with protocols includingAMBA AXI4, AHB, APB, and related interconnect standards.


• Integrate IPs such asPCIe, DDR, Ethernet, ARM/RISC-Vprocessors, and other SoC components.


• Handle clock, reset, configuration, power, and connectivity requirements across integrated designs.


• Perform RTL quality checks includinglint, CDC, RDC, andstructural verification.


• Work with tools such asSpyGlass, Questa CDC, VC SpyGlass, or equivalent static-analysis platforms.


• Develop and reviewSDC timing constraintsand collaboratewith Synthesis and Physical Design teamson timing requirements.


• Analyse synthesis, timing, area, and power results and resolve RTL-level integration issues.


• Implement functional and timingECOswhile maintaining design integrity.


• Develop automation scripts usingPython, TCL, Perl,or Shellto improve RTLintegration and verificationworkflows.


• Debug complex RTL, connectivity simulation, synthesis,and integration issues.


• Participate in architecture, design, code, and sign-off reviews.


• Collaborate with Design Verification, DFT, Physical Design, Synthesis, Architecture, and other engineering teams.


• Support design quality, integration milestones, sign-off activities, andtapeout readiness.


• Mentor junior engineers andcontribute to improving RTL integration methodologies and best practices.

WHAT MAKES YOU A GREAT FIT

• 7+ years of experiencein RTL design, RTL integration, SoC integration, or semiconductor product development.


• Strong hands-on expertise inRTL Integration and Verilog/SystemVerilog.


• Strongunderstanding of digital designconcepts, RTL coding, module hierarchy, interfaces, and SoC architecture.


• Proven experience integrating complexIPs and building large-scaleSoC/subsystem-level RTL.


• Strong knowledgeofAMBA protocols,including AXI, AHB, and APB.


• Experience with processor, memory, interconnect, PCIe, Ethernet, or other complex SoC IP integration.


• Strong understanding ofclock-domain crossing, reset-domain crossing, lint, structural checks, and low-power concepts.


• Experience with static verification andRTL-qualitytools such asSpyGlass, Questa CDC,or equivalent.


• Good understanding of synthesis, timing analysis,SDC constraints, and physical-design considerations.


• Experience handling functional and timingECOsand supporting tapeout activities.


• Strong scripting and automation skills usingPython, TCL, Perl, or Shell.


• Excellent debugging, analytical, and problem-solving abilities.


• Strong understanding of semiconductor development flows fromRTL integration through verification, synthesis, physical design, and tapeout.


• Ability to work effectively with cross-functional engineering teams and communicate technical issues clearly.


• Experience mentoring engineers and taking ownership of complex technical deliverables.


• Bachelors or Masters degreeinElectrical Engineering, Electronics& Communication, VLSI, Computer Engineering,or a related disciplineis preferred.