Senior RTL Engineer

Modernize Chip Solutions (MCS); Dadri; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A leading tech firm in India is seeking a skilled RTL Design Engineer with over 5 years of experience and strong expertise in RTL integration. The ideal candidate will handle clock domain crossing, synthesis, and ensure seamless integration of multiple IPs. Proficiency in Verilog/SystemVerilog and tools for CDC and RDC analysis is essential for this role, along with a solid understanding of SoC design flows. Immediate joiners are preferred, and this is an on-site opportunity.

Qualifications

• 5+ years of experience in RTL design and integration.
• Hands-on experience with CDC and RDC analysis.
• Proficiency in Verilog/SystemVerilog and synthesis tools.

Responsibilities

• Perform RTL design and integration at subsystem/SoC level.
• Handle clock domain crossing and reset domain crossing analysis.
• Work on synthesis, timing analysis, and optimization.
• Integrate multiple IPs for seamless functionality.
• Debug and resolve design issues across different stages.

Skills

RTL design and integration

CDC, RDC analysis and fixes

synthesis tools and timing closure

Verilog/SystemVerilog

SoC architecture understanding

Job description

Location:

Noida

Notice Period:

Immediate to 15 Days

Job Description:

We are looking for a skilled RTL Design Engineer with 5+ years of experience and strong expertise in RTL integration. The ideal candidate should have hands‑on experience in RDC, CDC, and synthesis, along with a solid understanding of SoC design flows.

Key Responsibilities:

• Perform RTL design and integration at subsystem/SoC level
• Handle clock domain crossing (CDC) and reset domain crossing (RDC) analysis and closure
• Work on synthesis, timing analysis, and optimization
• Integrate multiple IPs and ensure seamless functionality
• Debug and resolve design issues across different stages of the design cycleCollaborate with verification, physical design, and DFT teams

Required Skills & Expertise:

• Strong hands‑on experience in RTL design and integration
• Expertise in CDC, RDC analysis and fixes
• Good experience in synthesis tools and timing closure
• Proficiency in Verilog/SystemVerilog
• Understanding of SoC architecture and design methodologies
• Experience with Lint, STA, and low‑power checks is a plus