Senior Lead Engineer - Physical Design

MosChip Technologies Limited; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

MosChip Technologies Limited in Hyderabad is seeking a Senior Lead Physical Design Engineer to join our on-site team. You will lead physical design, physical verification, RTL design and related tasks for advanced silicon products, collaborating with front-end teams.

The role requires 12–15 years of PD experience, strong Cadence or Synopsys skills, and hands-on leadership for 7nm or smaller nodes with low power techniques. Excellent communication and mentoring abilities are essential.

Qualifications

• 12–15 years of experience in physical design
• Experience with 7nm or smaller nodes with low power techniques
• Proven leadership and mentoring abilities
• Proficiency with Cadence or Synopsys tools
• Strong cross-team communication and documentation

Responsibilities

• Lead a team of PD engineers and drive block closure
• Interface with front-end ASIC teams to resolve issues
• Drive timing closure for high-speed interfaces
• Provide technical guidance and mentoring to junior engineers

Skills

Block level PNR

Timing optimization

Physical design

Cadence/Synopsys

PERL/TCL scripting

Team leadership

Front-end interface

Education

BE/BTech in Electronics/EC

Tools

Cadence

Synopsys

Job description

MosChip® Technologies is a publicly traded company with expertise in SILICON | PRODUCT | AI/ML Engineering solutions. The company has 1250+ engineers located in Silicon Valley-USA and India. MosChip® offers end-to-end silicon design, verification, systems, software, and device engineering solutions, including AI/ML solution design and test automation.

Role Description:

This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products.

Qualifications:

• He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
• Minimum of 12-15 years of experience in physical design.
• He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
• Provide technical guidance, mentoring to physical design engineers.
• Lead a team of Physical design engineers and be responsible for their blocks’ closure
• Interface with front-end ASIC teams to resolve issues.
• Expertise in Timing closure on high speed interfaces is a plus
• Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.