Physical Design Engineer

Recruitrite; Hyderabad; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Recruitrite is assisting a product-based client in Hyderabad to hire an experienced engineer to lead pre-silicon SOC level design and front-end chip implementation. You will drive RTL coding, synthesis, netlist generation and timing checks, collaborating with Physical Design teams to ensure successful tape-out.

The role requires 6–13 years of hands-on ASIC design, strong leadership, communication and scripting skills in Perl/Tcl, plus floorplanning and DFT exposure. On-site in Hyderabad.

Qualifications

• 6–13 years of experience in complex ASIC design; SOC/Graphics/Video a plus.
• Deep knowledge of design process from spec to tape-out and post-Si debug.
• Hands-on experience in chip-level design/integration activities.

Responsibilities

• Lead pre-silicon SOC level design and frontend chip implementation from RTL to netlist.
• Oversee synthesis, netlisting, timing and LEC checks, floorplanning, and timing closure.
• Budgeting, clock methodology, and timing constraint management with Physical Design teams.
• Mentor junior engineers, provide technical leadership and guidance.

Skills

Team leadership

Mentoring

Communication

Analytical thinking

Scripting

Education

Bachelor’s or Master’s in Electrical or Computer Engineering

Tools

Cadence RTL Compiler

Design Compiler

PrimeTime

Conformal LEC

Perl

Tcl

Job description

This opportunity is with one of our client – Product based MNC.

The candidate will be responsible for leading the pre-silicon SOC level design. The candidate will also be responsible for Front-End chip implementation including design integration, synthesis and execution flows that starts with RTL coding and ends with the delivery of a netlist package ready for physical design. Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management. Candidate will work in collaboration with Physical Design Engineers in chip level planning and integrations.

Experience required: 6 to 13 Yrs.

Work location: Hyderabad.

Requirement:

• At least 4 years ( Master’s) or 6 Years’ experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.
• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
• Have hands-on experience in Chiplevel Design/Integration activities.
• Some Physical Design exposure required.
• Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
• Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
• Some exposure to DFT is a strong plus.
• Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.
• Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers is required.
• Should have proficiency in flow development and scripting.
• Expertise in Perl and Tcl is a must.
• Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
• Must have good communication & Analytical thinking skills.
• Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.

Bachelor/Master/ Degree in Electrical or Computer Engineering