Physical Design Engineer

MosChip®; Hyderabad; Sur place; INR 1 000 000 - 2 000 000; Plein temps

Résumé du poste

A leading semiconductor firm in Hyderabad is seeking an Executive for Talent Acquisition to focus on ASIC Physical Design. Candidates should have 7 to 20 years of experience and expertise in areas such as floor planning, timing optimization, and low-power design techniques. Strong mentoring and communication skills are essential, along with proficiency in industry-standard tools. This is a full-time position with a mid-senior level designation.

Qualifications

• 7 to 20 years of experience in talent acquisition.
• Experience with ASIC Physical Design is preferred.
• Ability to mentor and guide engineers.

Responsabilités

• Provide technical guidance to physical design engineers.
• Interface with ASIC teams to resolve issues.
• Ensure timing closure on interfaces.

Connaissances

Top-level floor planning

PG Planning

Clock tree synthesis

Timing analysis/closure

Low Power Design techniques

Physical Design Tools (Cadence/Synopsys/Magma)

Scripting (PERL, TCL)

Static Timing Analysis

Good communication skills

Description du poste

Overview

Executive- Talent Acquisition at MosChip Technologies

Experience: 7 to 20 Years

Shift: General (No WFH)

Work Week: Monday to Friday

Technical Skills :

He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.

• Provide technical guidance, mentoring to physical design engrs.
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
• Timing closure on DDR2/DDR3/PCIE interfaces.
• Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Research and Design

Industries

• Semiconductor Manufacturing