Technical Lead- Physical Design

eInfochips (An Arrow Company); Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

eInfochips (An Arrow Company) in Bengaluru seeks a Technical Lead for Physical Design to guide a small team and deliver block-level floorplanning and timing closure for advanced SoCs.

You will work across RTL-to-GDSII flows using ICC/Innovus, mentor 2–4 engineers, and collaborate with cross-functional teams to meet customer requirements.

Qualifications

• Extensive experience in ASIC physical design flow from RTL to GDSII.
• Experience leading 2-4 engineers and mentoring on the job.
• Hands-on with PNR tools and achieving timing closure.
• Experience with 65nm to 16nm technologies.

Responsibilities

• Lead floorplanning, timing constraints, physical synthesis and routing for blocks.
• Coordinate block-level place and route from Netlist through GDS flow.
• Ensure full chip implementation of complex SoCs (RTL-to-GDSII).
• Manage timing budgeting and close STA across corners and modes.
• Collaborate with design teams to close CTS, IO and DFT timing.
• Drive digital design automation and regression across RTL-to-GDSII.
• Deliver blocks to customers and interface with cross-teams for constraints.

Skills

Team leadership

Physical design

Floorplanning

Timing closure

Routing

Clock tree optimization

Scripting

DFT timing

Antennas and SI

Education

B.E./B.S./B.Tech./M.S./M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation

Tools

Synopsys ICC

Cadence Innovus

Cadence Encounter

Tcl

Perl

Shell scripting

Job description

POSITION TITLE: Technical Lead – Physical Design

POSITION SUMMARY

The candidate should have direct and first‑hand experience working in managing 4 -10 members engineering team – and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements).

ROLE & RESPONSIBILITIES

• Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR Flow
• will be responsible for executing the block level place and route assignments from Netlist through GDS flow
• Responsible for full chip implementation of complex SoCs (RTL-to-GDSII)
• To Coordinate all timing budgeting required for physical design task
• To close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
• Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing.
• Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
• To ensure successful delivery of his block(s) to customers
• To interface with other teams to understand design constraints, deliverable formats, customer requirements
• To contribute for enhancing the best practices of the physical design flow
• Should be able to lead 2-4 Engineers and ensuring their delivery including training (normal OR on the job), review and sign off.

ESSENTIAL SKILLS & EXPERIENCE

• Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry.
• Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player
• Hands‑on experience with Place and Route tools (Synopsys - ICC , Cadence – Innovus / Encounter) is a must.
• Experience on latest technology (28nm,16nm,7 nm)
• Consistent track record of successful tapeouts of high performance networking ASICs

EDUCATION BACKGROUND

B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering