Physical

Aritrak Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Aritrak Technologies is seeking a skilled Physical Design Engineer in Bengaluru to join the backend implementation team. You will lead RTL-to-GDSII implementation for complex SoCs, focusing on performance, power, and area optimization while ensuring signoff closure.

The role requires 4+ years in ASIC physical design, strong experience with Cadence Innovus and ICC2, and proficiency in Synopsys PrimeTime, Calibre, and related flows. Collaboration with RTL/DFT/STA teams is essential.

Qualifications

• B.E/B.Tech in Electronics, Electrical, or VLSI Design.
• 4+ years of experience in ASIC physical design.
• Strong hands-on experience with P&R tools and physical signoff flows.
• Familiarity with UPF/CPF-based low-power flows.
• Good understanding of floorplanning, CTS, routing, ECOs, and signoff.

Responsibilities

• Own block-level or full-chip implementation from RTL to GDSII.
• Perform floorplanning, placement, CTS, routing, and timing closure.
• Run and close STA, IR drop, EM, DRC, LVS, and antenna checks.
• Drive physical verification and signoff across corners.
• Collaborate with RTL, DFT, STA, and power teams for integration.
• Implement and debug low-power design techniques and timing fixes.

Skills

Place & Route

Timing Closure

CTS

Signoff

Floorplanning

Placement

Routing

Power/IR Drop

Scripting (Tcl/Perl/Python)

EDA Tools

Education

B.E./B.Tech in Electronics / Electrical / VLSI Design

M.E./M.Tech in Electronics / VLSI (optional)

Tools

Cadence Innovus

Synopsys ICC2

Siemens Nitro

Synopsys PrimeTime

Calibre

RedHawk

Tempus

Job description

Job Title: Physical Design Engineer

Experience: 4+ Years

Location: Banglaore/Hyderabad

Employment Type: Full-time

Industry: Semiconductors / VLSI / ASIC Design

Job Summary:

We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.

Key Responsibilities:

• Own block-level or full-chip implementation from RTL to GDSII.
• Perform:
• Floorplanning and placement
• Clock tree synthesis (CTS)
• Routing and optimization
• Run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks.
• Drive physical verification and signoff across various corners and scenarios.
• Collaborate with RTL, DFT, STA, and power teams for successful integration.
• Implement and debug low-power design techniques (UPF/CPF-based flows).
• Apply congestion analysis, ECOs, and timing fixes across critical paths.
• Optimize for performance, power, and area using EDA tools and foundry guidelines.
• Prepare design reports and support tapeout activities.

Required Skills and Experience:

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
• 4+years of experience in ASIC physical design.
• Strong hands-on experience with tools like:
• Place & Route: Cadence Innovus, Synopsys IC Compiler II (ICC2), Siemens Nitro
• STA: Synopsys PrimeTime
• Signoff: Calibre (DRC/LVS), RedHawk (IR/EM), Tempus
• Good understanding of physical design concepts: floorplan, placement, CTS, routing, ECO, and signoff.
• Familiarity with scripting languages: Tcl, Perl, Python for flow automation.
• Solid grasp of timing analysis, power grid design, and physical verification flows.