Senior Physical design manager

SignOff semiconductors; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

SignOff semiconductors is seeking an experienced Senior Physical Design Manager in Bangalore to lead the PD team across synthesis, timing, and physical closure. You will oversee block and subsystem implementations, collaborate with partner teams, and drive timing convergence, floorplanning, and power reduction initiatives.

The role requires a strong track record in PD leadership, excellent communication, and hands-on experience with 7nm and sub-7nm processes.

Qualifications

• 12+ years of experience in Physical Design with at least 2+ years of people management.
• Experience leading PD teams for complex SOC ASICs.
• Strong communication and presentation skills.
• Hands-on in Front-End design, DFX and PD flows.

Responsibilities

• Manage the team responsible for Synthesis, Physical Design, timing and physical closure.
• Lead a large team of internal and external resources.
• Ensure on-time delivery of SOC chip with high QOR.
• Oversee physical implementation of block and subsystem levels.
• Contribute to Synthesis, Power reduction, Timing convergence, floorplanning.

Skills

Team management

PD coordination

Synthesis & PD

Communication skills

DFX

Presentation skills

Education

BE/B.Tech/ME/M.Tech in ECE/EEE

Tools

Synopsys ICC2

ICC

Design Compiler

PrimeTime

StarRC

Mentor Calibre

Apache Redhawk

Job description

Job Description

Senior Physical Design Manager

Location: Bangalore

We are looking for an experienced SOC Physical Design Manager and deliver the next generation of cutting-edge graphics designs

KEY RESPONSIBILITIES:

• Manage the team responsible for Synthesis, Physical Design, timing and Physical closure
• Manage a large team of internal and external resources
• Responsible for ensuring the completion of the SOC chip on schedule with high QOR
• Physical implementation of block level and subsystem level
• Contribute to Synthesis, Power Reduction, Timing Convergence Floorplan efforts of block and subsystem

PREFERRED EXPERIENCE:

• Proven track record on successfully managing PD teams for complex SOC
• Have an in depth understanding and experience for all Physical Design activities for a large, leading technology SOC ASIC chip
• Have strong management, technical problem solving, communication and presentation skills
• Great team player able to effectively interact and collaborate with partner teams
• Experienced with Front-End design, DFX and Physical Design Flows
• Communication skills: excellent oral, written and presentation skills
• Extensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
• Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR
• Hands on experience on 7nm and sub-7nm projects
• Experienced in Full Chip Floorplaning, PNR Partitioning / Bump Placement is preferred
• Experience in Low power and high performance design.
• Responsible for on-time delivery of block-level layouts with exceptional quality.
• Strong self-driving ability & problem-solving skills with high drive for improvements
• Should have excellent communication skills (both written and oral)

ACADEMIC CREDENTIALS:

BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

12+ years of experience in Physical Design with atleast 2+ years of experience in people management