Physical Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A semiconductor design company in Bengaluru is seeking a Physical Design Engineer to manage full-chip/ block-level physical implementation of integrated circuits. The ideal candidate will have over 3 years of experience, expertise in industry-standard EDA tools, and a strong background in electrical or electronics engineering. This position offers a full-time contract with a mid-senior level employment type.

Qualifications

• 3+ years of experience in physical design.
• Proven track record of tape-outs in advanced process nodes.
• Expert proficiency in industry-standard EDA tools.

Responsibilities

• Own and execute phases of the physical design flow.
• Perform Static Timing Analysis and optimize design.
• Design and optimize the clock network.

Skills

Physical design expertise

Strong analytical skills

Experience with EDA tools

Collaborative skills

Education

Bachelor's or Master's in Electrical Engineering

Tools

Synopsys EDA tools

Cadence Innovus

Job description

Direct message the job poster from LeadSoc Technologies Pvt Ltd

The Physical Design Engineer will be responsible for the full-chip and/or block-level physical implementation of complex digital, mixed-signal, or RF integrated circuits from RTL to GDSII (the final manufacturing data). This role requires expertise in design methodologies to achieve optimal performance, power, and area (PPA) targets while ensuring manufacturability.

Key Responsibilities

• Physical Implementation Flow: Own and execute all phases of the physical design flow, including:
• Synthesis (RTL to Netlist).
• Floorplanning and Partitioning (defining block boundaries, pin placement, and power grid planning).
• Power Rail/Grid Design and analysis (EM/IR Drop).
• Place and Route (Placement of standard cells and macro blocks, followed by signal routing).
• Clock Tree Synthesis (CTS): Design and optimize the clock network for minimal skew and latency.
• Timing Closure: Perform Static Timing Analysis (STA), identify critical paths, and implement design optimization techniques (e.g., buffering, sizing, ECOs) to meet all frequency and timing constraints (setup/hold).

Required Qualifications and Skills

Education

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills & Experience

• Experience: 3+ years of experience in physical design, with a proven track record of tape-outs in advanced process nodes (e.g., 16nm, 7nm, 5nm, or lower).
• EDA Tools: Expert proficiency with industry-standard EDA tools from vendors like Synopsys (Fusion Compiler, ICC2, PrimeTime), Cadence (Innovus), or Mentor Graphics.

Soft Skills

• Excellent analytical, debugging, and problem-solving skills.
• Strong verbal and written communication skills.
• Ability to work effectively in a team environment and collaborate across different engineering disciplines.

Experience Level: 3yrs to 15yrs

Notice Period: Immediate to 60 Days

Mode of Work: WFO

Employment Type: Permanent

Job Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Design
• Industries: Semiconductor Manufacturing

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