Lead Engineer-Physical Design

MosChip Technologies Limited; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

MosChip Technologies Limited is looking for a Senior Lead Physical Design Engineer in Hyderabad. This full-time on-site role involves leading a team responsible for physical design tasks, including block-level PNR and timing closure on high-speed interfaces. The ideal candidate should have 7-15 years of experience, expertise in 7nm or lower node designs, and a strong command of tools like Cadence or Synopsys along with scripting skills. Effective communication and mentoring capabilities are essential for this position.

Qualifications

• 7-15 years of experience in physical design.
• Experience with 7nm or lower node designs.
• Expertise in timing closure and high-speed interfaces.

Responsibilities

• Responsible for physical design tasks.
• Lead a team of physical design engineers.
• Interface with front-end ASIC teams.

Skills

Physical design

Logic design

RTL design

Timing closure

Scripting (PERL, TCL)

Communication skills

Tools

Cadence

Synopsys

Job description

MosChip® Technologies is a publicly traded company with expertise in SILICON | PRODUCT | AI/ML Engineering solutions. The company has 1250+ engineers located in Silicon Valley-USA and India. MosChip® offers end-to-end silicon design, verification, systems, software, and device engineering solutions, including AI/ML solution design and test automation.

Role Description:

This is a full‑time on‑site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products.

Qualifications:

• He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan‑chain‑reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
• Minimum of 7-15 years of experience in physical design.
• He/She should have worked on 7nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating and substrate‑bias.
• Provide technical guidance, mentoring to physical design engineers.
• Lead a team of Physical design engineers and be responsible for their blocks’ closure.
• Interface with front‑end ASIC teams to resolve issues.
• Expertise in Timing closure on high speed interfaces is a plus.
• Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime‑SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.