Physical Design Engineer

Weekday; Hyderabad; On-site; INR 2,000,000 - 5,000,000; Full time

Job summary

Weekday is seeking an experienced Physical Design Engineer to drive high-performance ASIC/SoC silicon, translating complex RTL into manufacturable tape-out chips in Hyderabad, India. You will lead floorplanning, timing, and power optimization while mentoring junior engineers and improving design quality.

The role requires 8+ years in physical design, deep VLSI tooling expertise (IC Compiler, Calibre, Innovus, PrimeTime), and collaboration across synthesis, verification, and test teams.

Qualifications

• 8+ years of proven experience in physical design for ASIC/SoC projects.
• Strong command of VLSI layout tools and timing analysis techniques.
• Experience with floorplanning, clock tree synthesis, and power optimization.

Responsibilities

• Lead the physical design flow from floorplanning to tape-out for ASIC and SoC projects.
• Perform rigorous static timing analysis and resolve timing violations using industry tools such as Synopsys IC Compiler and PrimeTime.
• Optimize power consumption through leakage and dynamic power analysis and implement voltage scaling techniques.
• Interface with floorplanning and clock tree synthesis teams to balance area, timing, and power trade-offs.
• Conduct detailed layout verification using DRC, LVS, and parasitic extraction tools.
• Generate and maintain comprehensive design documentation, including mask data and physical design specifications.
• Coordinate with tape-out facilities to ensure correct fabrication data transfer and layout compliance.
• Analyze and debug manufacturing issues post-tape-out to identify process or design root causes.
• Participate in design reviews and provide constructive feedback to improve design quality.
• Stay updated on the latest VLSI physical design methodologies, tools, and industry best practices.

Skills

Physical design

VLSI layout

Static timing analysis

Power optimization

Mentoring

Teamwork

Education

Bachelor’s or Master’s degree in Electrical Engineering or VLSI Design

Tools

Synopsys IC Compiler

Mentor Calibre

Cadence Innovus

Synopsys PrimeTime

Parasitic extraction tools

Job description

This role is for one of the Weekday's clients

Salary range: Rs 2000000 - Rs 5000000 (ie INR 20-50 LPA)

Experience: 8+ yrs

Location: Hyderabad, Telangana, India

As a Physical Design Engineer, you will drive the creation of high-performance, low-power silicon solutions by translating complex RTL designs into manufacturable, taped-out chips. Leveraging your deep expertise in VLSI layout, you will optimize placement, clock tree synthesis, and routing while ensuring adherence to timing, power, and area constraints. Your role will involve close collaboration with synthesis, verification, and test teams to deliver designs that meet stringent performance and yield targets. You will also mentor junior engineers and contribute to process improvements that enhance productivity and design quality across the development lifecycle.

Key Responsibilities

• Lead the physical design flow from floorplanning to tape-out for ASIC and SoC projects.
• Perform rigorous static timing analysis and resolve timing violations using industry tools such as Synopsys IC Compiler and PrimeTime.
• Optimize power consumption through leakage and dynamic power analysis and implement voltage scaling techniques.
• Interface with floorplanning and clock tree synthesis teams to balance area, timing, and power trade‑offs.
• Conduct detailed layout verification using DRC, LVS, and parasitic extraction tools.
• Generate and maintain comprehensive design documentation, including mask data and physical design specifications.
• Coordinate with tape‑out facilities to ensure correct fabrication data transfer and layout compliance.
• Analyze and debug manufacturing issues post‑tape‑out to identify process or design root causes.
• Participate in design reviews and provide constructive feedback to improve design quality.
• Stay updated on the latest VLSI physical design methodologies, tools, and industry best practices.

What Makes You a Great Fit

• 8+ years of proven experience in physical design for complex ASIC or SoC projects.
• Strong command of VLSI layout tools, particularly Synopsys IC Compiler, Mentor Calibre, and Cadence Innovus.
• Deep knowledge of static timing analysis techniques using Synopsys PrimeTime or equivalent.
• Proficiency in power analysis and optimization, including implementation of power‑gating and clock‑domain crossing strategies.
• Demonstrated experience with DRC/LVS verification and parasitic extraction workflows.
• Excellent problem‑solving skills with a track record of resolving critical timing and layout issues under tight deadlines.
• Strong communication and teamwork abilities, capable of collaborating across multi-disciplinary engineering teams.
• Familiarity with EUV and 14nm/7nm process design kits and related manufacturing constraints.
• Ability to mentor junior engineers and contribute to process enhancement initiatives.
• Holds a Bachelor’s or Master’s degree in Electrical Engineering, VLSI Design, or a related field.