Senior/Lead Physical Design Engineer

Eximietas Design LLC; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Eximietas Design LLC in Bengaluru is seeking a Senior/Lead Physical Design Engineer to lead the development and implementation of physical design flows for complex ASICs.

The role requires 3–10 years of hands-on experience, and you will mentor juniors, collaborate with RTL/DFT teams, and drive timing, power, and area targets to deliver high‑quality designs on schedule.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications.
• 3–10 years of experience in physical design of ASICs.
• Proficiency with Cadence, Synopsys, and Mentor Graphics for Synthesis, PnR and Signoff.
• Strong timing, power optimization experience.
• Solid scripting skills in TCL, Python, or Perl for automation.
• Excellent communication and teamwork abilities.

Responsibilities

• Perform synthesis, floorplanning, placement, clock, routing and PPA optimization for high-speed ASICs.
• Define and drive physical design strategies to meet performance, power and area targets.
• Analyze timing, power and area and drive design optimizations for QoR.
• Lead signoff closures for STA, PV, LEC, IR/EM, CLP efficiently.
• Provide technical leadership and mentor junior engineers.
• Collaborate with RTL and DFT teams to meet design constraints.
• Develop and refine advanced physical design methodologies and flows.

Skills

Synthesis

Floorplanning

Placement

Clock tree optimization

Routing

PPA optimization

Timing closure

Power optimization

TCL/Python/Perl scripting

Mentoring

Education

Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications

Tools

Cadence

Synopsys

Mentor Graphics

DC/Genus tools

Job description

Job Title: Senior/Lead Physical Design Engineer
Location: BangaloreExperience: 3 – 10 years

Job Overview: We are seeking an exceptional Senior/Lead Physical Design Engineer to take a key role in our semiconductor design team. As a Senior/Lead Physical Design Engineer, you will lead the development and implementation of cutting‑edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross‑functional teams to ensure the successful delivery of high‑quality designs.

Responsibilities:

• Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.
• Define and drive physical design strategies to meet aggressive performance, power, and area targets.
• Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR.
• Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently.
• Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence.
• Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs.
• Support and Development of advanced physical design methodologies and flows for complex semiconductor designs.

Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications.
• 3 – 10 years of experience in physical design of ASICs
• Proficiency in industry‑standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure.
• Extensive experience with timing closure techniques, power optimization.
• Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
• Excellent problem‑solving and analytical skills, with a track record of delivering high‑quality designs on schedule.
• Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
• Proven ability to lead and mentor junior engineers, fostering their professional growth and development.

Preferred qualifications:

• Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
• Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues.
• Experience in handling Partitions and blocks for size estimation, pin assignment, CTS.
• Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration.
• Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power.
• Familiarity with low‑power design techniques and methodologies, such as multi‑voltage domains and power gating using UPF.
• Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks.
• Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues.
• Experience with formal verification for RTL to Netlist and Netlist to Netlist.
• Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.