Senior Engineer - Physical Design

MosChip Technologies Limited; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

MosChip Technologies Limited is seeking an experienced ASIC Physical Design engineer to lead block- and top-level floor planning, partitioning and P&R tasks in advanced node flows.

The role requires hands-on expertise in timing closure, SI/IR drop analysis, DRC/LVS, clock tree synthesis, extraction, and ECOs, with a strong background in Cadence, Synopsys or Magma tools. You will mentor juniors, interface with front-end teams, and drive design rule checks to ensure tape-out readiness.

Qualifications

• Experience with 4–5nm, 28nm or lower node designs and low power techniques.
• Strong background in ASIC Physical Design lifecycle and flow.
• Proficiency in CAD/EDA tools and scripting for automation.
• Ability to mentor and guide junior team members.

Responsibilities

• Perform block- and top-level floor planning, PG planning, and partitioning for hierarchical designs.
• Handle placement, scan-chain reordering, clock tree synthesis, timing optimization, and SI-aware routing.
• Conduct timing analysis/closure, ECO tasks, SI/DRC/LVS checks, antennas, and fix violations.
• Interface with front-end ASIC teams, and provide technical guidance to peers.

Skills

ASIC Physical Design

Floor planning

Timing analysis

Perl scripting

TCL scripting

Tools

Cadence

Synopsys

Magma

Job description

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.

Provide technical guidance, mentoring to physical design eng inee rs.

Interface with front-end ASIC teams to resolve issues.

Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.

Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.

Expertise in scripting languages such as PERL, TCL.

Strong Physical Verification skill set.

Static Timing Analysis in Primetime or Primetime-SI.

Good written and oral communication skills. Ability to clearly document plans.

Ability to interface with different teams and prioritize work based on project needs.